Searched refs:max_ref_div (Results 1 – 7 of 7) sorted by relevance
990 ref_div_max = min(pll->max_ref_div, 7u); in radeon_compute_pll_avivo()992 ref_div_max = pll->max_ref_div; in radeon_compute_pll_avivo()1115 uint32_t max_ref_div = pll->max_ref_div; in radeon_compute_pll_legacy() local1131 DRM_DEBUG_KMS("PLL freq %"PRIu64" %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); in radeon_compute_pll_legacy()1146 min_ref_div = max_ref_div = pll->reference_div; in radeon_compute_pll_legacy()1148 while (min_ref_div < max_ref_div-1) { in radeon_compute_pll_legacy()1149 uint32_t mid = (min_ref_div + max_ref_div) / 2; in radeon_compute_pll_legacy()1152 max_ref_div = mid; in radeon_compute_pll_legacy()1187 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { in radeon_compute_pll_legacy()
310 dcpll->max_ref_div = 0x3ff; in radeon_get_clock_info()316 p1pll->max_ref_div = 0x3ff; in radeon_get_clock_info()322 p2pll->max_ref_div = 0x3ff; in radeon_get_clock_info()331 spll->max_ref_div = 0xff; in radeon_get_clock_info()340 mpll->max_ref_div = 0xff; in radeon_get_clock_info()
186 uint32_t max_ref_div; member
394 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()417 mpll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
157 ref_div_max = pll->max_ref_div; in amdgpu_pll_compute()
211 uint32_t max_ref_div; member
614 ppll->max_ref_div = 0x3ff; in amdgpu_atombios_get_clock_info()644 spll->max_ref_div = 0xff; in amdgpu_atombios_get_clock_info()676 mpll->max_ref_div = 0xff; in amdgpu_atombios_get_clock_info()