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Searched refs:le32_to_cpu (Results 1 – 25 of 108) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_ucode.c40 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); in amdgpu_ucode_print_common_hdr()
41 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); in amdgpu_ucode_print_common_hdr()
46 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); in amdgpu_ucode_print_common_hdr()
47 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); in amdgpu_ucode_print_common_hdr()
49 le32_to_cpu(hdr->ucode_array_offset_bytes)); in amdgpu_ucode_print_common_hdr()
50 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); in amdgpu_ucode_print_common_hdr()
66 le32_to_cpu(mc_hdr->io_debug_size_bytes)); in amdgpu_ucode_print_mc_hdr()
68 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); in amdgpu_ucode_print_mc_hdr()
86 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); in amdgpu_ucode_print_smc_hdr()
93 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes)); in amdgpu_ucode_print_smc_hdr()
[all …]
H A Damdgpu_discovery.c189 if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) { in amdgpu_discovery_init()
212 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { in amdgpu_discovery_init()
309 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); in amdgpu_discovery_reg_base_init()
392 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); in amdgpu_discovery_get_gfx_info()
393 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
394 le32_to_cpu(gc_info->gc_num_wgp1_per_sa)); in amdgpu_discovery_get_gfx_info()
395 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
396 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
397 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
398 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); in amdgpu_discovery_get_gfx_info()
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H A Damdgpu_rlc.c207 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in amdgpu_gfx_rlc_setup_cp_table()
208 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()
209 table_size = le32_to_cpu(hdr->jt_size); in amdgpu_gfx_rlc_setup_cp_table()
215 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in amdgpu_gfx_rlc_setup_cp_table()
216 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()
217 table_size = le32_to_cpu(hdr->jt_size); in amdgpu_gfx_rlc_setup_cp_table()
223 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in amdgpu_gfx_rlc_setup_cp_table()
224 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()
225 table_size = le32_to_cpu(hdr->jt_size); in amdgpu_gfx_rlc_setup_cp_table()
231 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in amdgpu_gfx_rlc_setup_cp_table()
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H A Damdgpu_psp_v11_0.c122 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); in psp_v11_0_init_microcode()
123 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); in psp_v11_0_init_microcode()
124 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); in psp_v11_0_init_microcode()
125 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); in psp_v11_0_init_microcode()
127 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); in psp_v11_0_init_microcode()
129 le32_to_cpu(sos_hdr->sos_offset_bytes); in psp_v11_0_init_microcode()
132 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); in psp_v11_0_init_microcode()
134 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); in psp_v11_0_init_microcode()
135 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); in psp_v11_0_init_microcode()
137 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); in psp_v11_0_init_microcode()
[all …]
H A Damdgpu_psp_v10_0.c84 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); in psp_v10_0_init_microcode()
85 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); in psp_v10_0_init_microcode()
86 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); in psp_v10_0_init_microcode()
88 le32_to_cpu(hdr->header.ucode_array_offset_bytes); in psp_v10_0_init_microcode()
106 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); in psp_v10_0_init_microcode()
108 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); in psp_v10_0_init_microcode()
111 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); in psp_v10_0_init_microcode()
113 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); in psp_v10_0_init_microcode()
116 le32_to_cpu(ta_hdr->ta_dtm_ucode_version); in psp_v10_0_init_microcode()
118 le32_to_cpu(ta_hdr->ta_dtm_size_bytes); in psp_v10_0_init_microcode()
[all …]
H A Damdgpu_mes_v10_1.c98 adev->mes.ucode_fw_version = le32_to_cpu(mes_hdr->mes_ucode_version); in mes_v10_1_init_microcode()
100 le32_to_cpu(mes_hdr->mes_ucode_data_version); in mes_v10_1_init_microcode()
102 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | in mes_v10_1_init_microcode()
103 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); in mes_v10_1_init_microcode()
105 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | in mes_v10_1_init_microcode()
106 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); in mes_v10_1_init_microcode()
128 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); in mes_v10_1_allocate_ucode_buffer()
129 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); in mes_v10_1_allocate_ucode_buffer()
160 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); in mes_v10_1_allocate_ucode_data_buffer()
161 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); in mes_v10_1_allocate_ucode_data_buffer()
H A Damdgpu_atomfirmware.c49 if (le32_to_cpu(firmware_info->firmware_capability) & in amdgpu_atomfirmware_gpu_supports_virtualization()
69 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); in amdgpu_atomfirmware_scratch_regs_init()
86 le32_to_cpu(firmware_usage->start_address_in_kb), in amdgpu_atomfirmware_allocate_fb_scratch()
90 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb); in amdgpu_atomfirmware_allocate_fb_scratch()
301 (le32_to_cpu(umc_info->v31.umc_config) & in amdgpu_atomfirmware_mem_ecc_supported()
335 (le32_to_cpu(firmware_info->v31.firmware_capability) & in amdgpu_atomfirmware_sram_ecc_supported()
365 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz); in amdgpu_atomfirmware_get_clock_info()
367 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz); in amdgpu_atomfirmware_get_clock_info()
374 le32_to_cpu(firmware_info->v31.firmware_capability); in amdgpu_atomfirmware_get_clock_info()
388 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
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H A Damdgpu_cgs.c229 data_size = le32_to_cpu(header->header.ucode_size_bytes); in amdgpu_cgs_get_firmware_info()
233 gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE); in amdgpu_cgs_get_firmware_info()
234 data_size = le32_to_cpu(header->jt_size) << 2; in amdgpu_cgs_get_firmware_info()
240 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version); in amdgpu_cgs_get_firmware_info()
243 info->image_size = le32_to_cpu(header->jt_offset) << 2; in amdgpu_cgs_get_firmware_info()
246 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version); in amdgpu_cgs_get_firmware_info()
465 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); in amdgpu_cgs_get_firmware_info()
471 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); in amdgpu_cgs_get_firmware_info()
472 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); in amdgpu_cgs_get_firmware_info()
473 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); in amdgpu_cgs_get_firmware_info()
[all …]
H A Damdgpu_psp_v3_1.c94 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); in psp_v3_1_init_microcode()
95 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); in psp_v3_1_init_microcode()
96 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); in psp_v3_1_init_microcode()
97 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - in psp_v3_1_init_microcode()
98 le32_to_cpu(hdr->sos_size_bytes); in psp_v3_1_init_microcode()
100 le32_to_cpu(hdr->header.ucode_array_offset_bytes); in psp_v3_1_init_microcode()
102 le32_to_cpu(hdr->sos_offset_bytes); in psp_v3_1_init_microcode()
114 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); in psp_v3_1_init_microcode()
115 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); in psp_v3_1_init_microcode()
116 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); in psp_v3_1_init_microcode()
[all …]
H A Damdgpu_navi10_ih.c219 wptr = le32_to_cpu(*ih->wptr_cpu); in navi10_ih_get_wptr()
264 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in navi10_ih_decode_iv()
265 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in navi10_ih_decode_iv()
266 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in navi10_ih_decode_iv()
267 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in navi10_ih_decode_iv()
268 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); in navi10_ih_decode_iv()
269 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); in navi10_ih_decode_iv()
270 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); in navi10_ih_decode_iv()
271 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); in navi10_ih_decode_iv()
H A Damdgpu_vcn.c132 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); in amdgpu_vcn_sw_init()
140 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf; in amdgpu_vcn_sw_init()
144 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff; in amdgpu_vcn_sw_init()
145 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff; in amdgpu_vcn_sw_init()
147 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; in amdgpu_vcn_sw_init()
148 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; in amdgpu_vcn_sw_init()
154 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; in amdgpu_vcn_sw_init()
155 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; in amdgpu_vcn_sw_init()
156 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; in amdgpu_vcn_sw_init()
163 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_vcn_sw_init()
[all …]
H A Damdgpu_gfx_v10_0.c610 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in gfx_v10_0_init_rlc_ext_microcode()
611 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in gfx_v10_0_init_rlc_ext_microcode()
612 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in gfx_v10_0_init_rlc_ext_microcode()
613 …adev->gfx.rlc.save_restore_list_cntl = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_lis… in gfx_v10_0_init_rlc_ext_microcode()
614 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in gfx_v10_0_init_rlc_ext_microcode()
615 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in gfx_v10_0_init_rlc_ext_microcode()
616 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in gfx_v10_0_init_rlc_ext_microcode()
617 …adev->gfx.rlc.save_restore_list_gpm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list… in gfx_v10_0_init_rlc_ext_microcode()
618 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); in gfx_v10_0_init_rlc_ext_microcode()
619 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); in gfx_v10_0_init_rlc_ext_microcode()
[all …]
H A Damdgpu_si_ih.c115 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
136 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in si_ih_decode_iv()
137 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in si_ih_decode_iv()
138 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in si_ih_decode_iv()
139 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in si_ih_decode_iv()
H A Damdgpu_cik_ih.c197 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
254 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in cik_ih_decode_iv()
255 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in cik_ih_decode_iv()
256 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in cik_ih_decode_iv()
257 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in cik_ih_decode_iv()
H A Damdgpu_iceland_ih.c199 wptr = le32_to_cpu(*ih->wptr_cpu); in iceland_ih_get_wptr()
233 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in iceland_ih_decode_iv()
234 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in iceland_ih_decode_iv()
235 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in iceland_ih_decode_iv()
236 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in iceland_ih_decode_iv()
H A Damdgpu_cz_ih.c199 wptr = le32_to_cpu(*ih->wptr_cpu); in cz_ih_get_wptr()
233 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in cz_ih_decode_iv()
234 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in cz_ih_decode_iv()
235 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in cz_ih_decode_iv()
236 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in cz_ih_decode_iv()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_ppatomfwctrl.c136 le32_to_cpu(voltage_object->gpio_voltage_obj. in pp_atomfwctrl_get_voltage_table_v4()
142 le32_to_cpu( in pp_atomfwctrl_get_voltage_table_v4()
271 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
272 dividers->ulDid = le32_to_cpu(pll_output->dfs_did); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
273 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
274 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
302 param->ulMaxVddc = le32_to_cpu(profile->maxvddc); in pp_atomfwctrl_get_avfs_information()
303 param->ulMinVddc = le32_to_cpu(profile->minvddc); in pp_atomfwctrl_get_avfs_information()
305 le32_to_cpu(profile->avfs_meannsigma_acontant0); in pp_atomfwctrl_get_avfs_information()
307 le32_to_cpu(profile->avfs_meannsigma_acontant1); in pp_atomfwctrl_get_avfs_information()
[all …]
H A Damdgpu_ppatomctrl.c346 le32_to_cpu(mpll_parameters.ulClock.ulClock); in atomctrl_get_memory_pll_dividers_ai()
369 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
395 le32_to_cpu(pll_patameters.ulClock.ulClock); in atomctrl_get_engine_pll_dividers_vi()
465 le32_to_cpu(pll_patameters.ulClock.ulClock); in atomctrl_get_dfs_pll_dividers_vi()
561 le32_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].ulVoltageId); in atomctrl_get_voltage_table_v3()
565 le32_to_cpu(voltage_object->asGpioVoltageObj.ulGpioMaskVal); in atomctrl_get_voltage_table_v3()
703 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM1), 1000); in atomctrl_calculate_voltage_evv_on_sclk()
707 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM2), 1000); in atomctrl_calculate_voltage_evv_on_sclk()
711 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM3), 1000); in atomctrl_calculate_voltage_evv_on_sclk()
715 fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM4), 1000); in atomctrl_calculate_voltage_evv_on_sclk()
[all …]
H A Damdgpu_process_pptables_v1_0.c224 = le32_to_cpu(atom_ppm_table->ulPlatformTDP); in get_platform_power_management_table()
226 = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDP); in get_platform_power_management_table()
228 = le32_to_cpu(atom_ppm_table->ulPlatformTDC); in get_platform_power_management_table()
230 = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDC); in get_platform_power_management_table()
232 = le32_to_cpu(atom_ppm_table->ulApuTDP); in get_platform_power_management_table()
234 = le32_to_cpu(atom_ppm_table->ulDGpuTDP); in get_platform_power_management_table()
236 = le32_to_cpu(atom_ppm_table->ulDGpuUlvPower); in get_platform_power_management_table()
238 = le32_to_cpu(atom_ppm_table->ulTjmax); in get_platform_power_management_table()
363 limits->sclk = le32_to_cpu(limitable->entries[0].ulSCLKLimit); in get_hard_limits()
364 limits->mclk = le32_to_cpu(limitable->entries[0].ulMCLKLimit); in get_hard_limits()
[all …]
H A Damdgpu_processpptables.c698 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
703 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
708 ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
716 rrr_index = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
733 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
738 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
743 ps->memory.m3arb = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
752 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
757 tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
765 ps->uvd_clocks.VCLK = le32_to_cpu(pnon_clock_info->ulVCLK); in init_non_clock_fields()
[all …]
H A Damdgpu_vega10_processpptables.c336 le32_to_cpu(powerplay_table->ulMaxODEngineClock); in init_over_drive_limits()
338 le32_to_cpu(powerplay_table->ulMaxODMemoryClock); in init_over_drive_limits()
373 le32_to_cpu(mm_dependency_record->ulPSPClk); in get_mm_clock_voltage_table()
374 mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk); in get_mm_clock_voltage_table()
375 mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk); in get_mm_clock_voltage_table()
376 mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk); in get_mm_clock_voltage_table()
544 tdp_table->ulBoostClock = le32_to_cpu(power_tune_table_v3->ulBoostClock); in get_tdp_table()
600 le32_to_cpu(clk_dep_table->entries[i].ulClk); in get_socclk_voltage_dependency_table()
638 le32_to_cpu(mclk_dep_table->entries[i].ulMemClk); in get_mclk_voltage_dependency_table()
676 le32_to_cpu(clk_dep_table->entries[i].ulClk); in get_gfxclk_voltage_dependency_table()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ucode.c38 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); in radeon_ucode_print_common_hdr()
39 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); in radeon_ucode_print_common_hdr()
44 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); in radeon_ucode_print_common_hdr()
45 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); in radeon_ucode_print_common_hdr()
47 le32_to_cpu(hdr->ucode_array_offset_bytes)); in radeon_ucode_print_common_hdr()
48 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); in radeon_ucode_print_common_hdr()
64 le32_to_cpu(mc_hdr->io_debug_size_bytes)); in radeon_ucode_print_mc_hdr()
66 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); in radeon_ucode_print_mc_hdr()
84 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); in radeon_ucode_print_smc_hdr()
103 le32_to_cpu(gfx_hdr->ucode_feature_version)); in radeon_ucode_print_gfx_hdr()
[all …]
H A Dradeon_vce_v1_0.c186 for (i = 0; i < le32_to_cpu(sign->num); ++i) { in vce_v1_0_load_fw()
187 if (le32_to_cpu(sign->val[i].chip_id) == chip_id) in vce_v1_0_load_fw()
191 if (i == le32_to_cpu(sign->num)) in vce_v1_0_load_fw()
199 data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64); in vce_v1_0_load_fw()
204 data += (le32_to_cpu(sign->len) + 64) / 4; in vce_v1_0_load_fw()
210 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); in vce_v1_0_load_fw()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
H A Dsoc15_int.h37 #define SOC15_CLIENT_ID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) & 0xff)
38 #define SOC15_SOURCE_ID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) >> 8 & 0xff)
39 #define SOC15_RING_ID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) >> 16 & 0xff)
40 #define SOC15_VMID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) >> 24 & 0xf)
41 #define SOC15_VMID_TYPE_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) >> 31 & 0x1)
42 #define SOC15_PASID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[3]) & 0xffff)
43 #define SOC15_CONTEXT_ID0_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[4]))
44 #define SOC15_CONTEXT_ID1_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[5]))
45 #define SOC15_CONTEXT_ID2_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[6]))
46 #define SOC15_CONTEXT_ID3_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[7]))
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
H A Damdgpu_bios_parser.c363 info->acpi_device = le32_to_cpu(device_tag->ulACPIDeviceEnum); in bios_parser_get_device_tag()
449 le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10; in get_firmware_info_v1_4()
451 le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10; in get_firmware_info_v1_4()
500 le32_to_cpu(firmwareInfo->ulMinPixelClockPLL_Output) * 10; in get_firmware_info_v2_1()
502 le32_to_cpu(firmwareInfo->ulMaxPixelClockPLL_Output) * 10; in get_firmware_info_v2_1()
504 le32_to_cpu(firmwareInfo->ulDefaultDispEngineClkFreq) * 10; in get_firmware_info_v2_1()
586 le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10; in get_firmware_info_v2_2()
588 le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10; in get_firmware_info_v2_2()
590 le32_to_cpu(firmware_info->ulDefaultDispEngineClkFreq) * 10; in get_firmware_info_v2_2()
647 (uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10); in get_firmware_info_v2_2()
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