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Searched refs:hsync_width (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_encoders.c178 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; in amdgpu_panel_mode_fixup() local
189 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in amdgpu_panel_mode_fixup()
202 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; in amdgpu_panel_mode_fixup()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_encoders.c339 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; in radeon_panel_mode_fixup() local
352 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in radeon_panel_mode_fixup()
367 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; in radeon_panel_mode_fixup()
/netbsd-src/sys/arch/arm/imx/
H A Dimx51_ipuv3var.h64 short hsync_width; member
H A Dimx51_ipuv3.c414 __DI_SW_GEN0(geom->panel_width + geom->hsync_width + in imx51_ipuv3_di_init()
421 __DI_SW_GEN0(geom->panel_width + geom->hsync_width + in imx51_ipuv3_di_init()
423 __DI_SW_GEN1(1, 1, 0, geom->hsync_width * 2, 1, 0, 0), in imx51_ipuv3_di_init()
445 __DI_SW_GEN0(0, 1, geom->hsync_width + geom->left, 1), in imx51_ipuv3_di_init()
/netbsd-src/sys/arch/evbarm/netwalker/
H A Dnetwalker_lcd.c108 .hsync_width = 8,
/netbsd-src/sys/external/bsd/drm2/dist/drm/
H A Ddrm_edid.c5033 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; in drm_mode_displayid_detailed() local
5047 mode->hsync_end = mode->hsync_start + hsync_width; in drm_mode_displayid_detailed()