xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_encoders.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1*41ec0267Sriastradh /*	$NetBSD: amdgpu_encoders.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $	*/
2efa246c0Sriastradh 
3efa246c0Sriastradh /*
4efa246c0Sriastradh  * Copyright 2007-8 Advanced Micro Devices, Inc.
5efa246c0Sriastradh  * Copyright 2008 Red Hat Inc.
6efa246c0Sriastradh  *
7efa246c0Sriastradh  * Permission is hereby granted, free of charge, to any person obtaining a
8efa246c0Sriastradh  * copy of this software and associated documentation files (the "Software"),
9efa246c0Sriastradh  * to deal in the Software without restriction, including without limitation
10efa246c0Sriastradh  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11efa246c0Sriastradh  * and/or sell copies of the Software, and to permit persons to whom the
12efa246c0Sriastradh  * Software is furnished to do so, subject to the following conditions:
13efa246c0Sriastradh  *
14efa246c0Sriastradh  * The above copyright notice and this permission notice shall be included in
15efa246c0Sriastradh  * all copies or substantial portions of the Software.
16efa246c0Sriastradh  *
17efa246c0Sriastradh  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18efa246c0Sriastradh  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19efa246c0Sriastradh  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20efa246c0Sriastradh  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21efa246c0Sriastradh  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22efa246c0Sriastradh  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23efa246c0Sriastradh  * OTHER DEALINGS IN THE SOFTWARE.
24efa246c0Sriastradh  *
25efa246c0Sriastradh  * Authors: Dave Airlie
26efa246c0Sriastradh  *          Alex Deucher
27efa246c0Sriastradh  */
28efa246c0Sriastradh 
29*41ec0267Sriastradh #include <sys/cdefs.h>
30*41ec0267Sriastradh __KERNEL_RCSID(0, "$NetBSD: amdgpu_encoders.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $");
31*41ec0267Sriastradh 
32efa246c0Sriastradh #include <drm/drm_crtc_helper.h>
33efa246c0Sriastradh #include <drm/amdgpu_drm.h>
34efa246c0Sriastradh #include "amdgpu.h"
35efa246c0Sriastradh #include "amdgpu_connectors.h"
36*41ec0267Sriastradh #include "amdgpu_display.h"
37efa246c0Sriastradh #include "atom.h"
38efa246c0Sriastradh #include "atombios_encoders.h"
39efa246c0Sriastradh 
40efa246c0Sriastradh void
amdgpu_link_encoder_connector(struct drm_device * dev)41efa246c0Sriastradh amdgpu_link_encoder_connector(struct drm_device *dev)
42efa246c0Sriastradh {
43efa246c0Sriastradh 	struct amdgpu_device *adev = dev->dev_private;
44efa246c0Sriastradh 	struct drm_connector *connector;
45*41ec0267Sriastradh 	struct drm_connector_list_iter iter;
46efa246c0Sriastradh 	struct amdgpu_connector *amdgpu_connector;
47efa246c0Sriastradh 	struct drm_encoder *encoder;
48efa246c0Sriastradh 	struct amdgpu_encoder *amdgpu_encoder;
49efa246c0Sriastradh 
50*41ec0267Sriastradh 	drm_connector_list_iter_begin(dev, &iter);
51efa246c0Sriastradh 	/* walk the list and link encoders to connectors */
52*41ec0267Sriastradh 	drm_for_each_connector_iter(connector, &iter) {
53efa246c0Sriastradh 		amdgpu_connector = to_amdgpu_connector(connector);
54efa246c0Sriastradh 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
55efa246c0Sriastradh 			amdgpu_encoder = to_amdgpu_encoder(encoder);
56efa246c0Sriastradh 			if (amdgpu_encoder->devices & amdgpu_connector->devices) {
57*41ec0267Sriastradh 				drm_connector_attach_encoder(connector, encoder);
58efa246c0Sriastradh 				if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
59efa246c0Sriastradh 					amdgpu_atombios_encoder_init_backlight(amdgpu_encoder, connector);
60efa246c0Sriastradh 					adev->mode_info.bl_encoder = amdgpu_encoder;
61efa246c0Sriastradh 				}
62efa246c0Sriastradh 			}
63efa246c0Sriastradh 		}
64efa246c0Sriastradh 	}
65*41ec0267Sriastradh 	drm_connector_list_iter_end(&iter);
66efa246c0Sriastradh }
67efa246c0Sriastradh 
amdgpu_encoder_set_active_device(struct drm_encoder * encoder)68efa246c0Sriastradh void amdgpu_encoder_set_active_device(struct drm_encoder *encoder)
69efa246c0Sriastradh {
70efa246c0Sriastradh 	struct drm_device *dev = encoder->dev;
71efa246c0Sriastradh 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
72efa246c0Sriastradh 	struct drm_connector *connector;
73*41ec0267Sriastradh 	struct drm_connector_list_iter iter;
74efa246c0Sriastradh 
75*41ec0267Sriastradh 	drm_connector_list_iter_begin(dev, &iter);
76*41ec0267Sriastradh 	drm_for_each_connector_iter(connector, &iter) {
77efa246c0Sriastradh 		if (connector->encoder == encoder) {
78efa246c0Sriastradh 			struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
79efa246c0Sriastradh 			amdgpu_encoder->active_device = amdgpu_encoder->devices & amdgpu_connector->devices;
80efa246c0Sriastradh 			DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
81efa246c0Sriastradh 				  amdgpu_encoder->active_device, amdgpu_encoder->devices,
82efa246c0Sriastradh 				  amdgpu_connector->devices, encoder->encoder_type);
83efa246c0Sriastradh 		}
84efa246c0Sriastradh 	}
85*41ec0267Sriastradh 	drm_connector_list_iter_end(&iter);
86efa246c0Sriastradh }
87efa246c0Sriastradh 
88efa246c0Sriastradh struct drm_connector *
amdgpu_get_connector_for_encoder(struct drm_encoder * encoder)89efa246c0Sriastradh amdgpu_get_connector_for_encoder(struct drm_encoder *encoder)
90efa246c0Sriastradh {
91efa246c0Sriastradh 	struct drm_device *dev = encoder->dev;
92efa246c0Sriastradh 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
93*41ec0267Sriastradh 	struct drm_connector *connector, *found = NULL;
94*41ec0267Sriastradh 	struct drm_connector_list_iter iter;
95efa246c0Sriastradh 	struct amdgpu_connector *amdgpu_connector;
96efa246c0Sriastradh 
97*41ec0267Sriastradh 	drm_connector_list_iter_begin(dev, &iter);
98*41ec0267Sriastradh 	drm_for_each_connector_iter(connector, &iter) {
99efa246c0Sriastradh 		amdgpu_connector = to_amdgpu_connector(connector);
100*41ec0267Sriastradh 		if (amdgpu_encoder->active_device & amdgpu_connector->devices) {
101*41ec0267Sriastradh 			found = connector;
102*41ec0267Sriastradh 			break;
103efa246c0Sriastradh 		}
104*41ec0267Sriastradh 	}
105*41ec0267Sriastradh 	drm_connector_list_iter_end(&iter);
106*41ec0267Sriastradh 	return found;
107efa246c0Sriastradh }
108efa246c0Sriastradh 
109efa246c0Sriastradh struct drm_connector *
amdgpu_get_connector_for_encoder_init(struct drm_encoder * encoder)110efa246c0Sriastradh amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder)
111efa246c0Sriastradh {
112efa246c0Sriastradh 	struct drm_device *dev = encoder->dev;
113efa246c0Sriastradh 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
114*41ec0267Sriastradh 	struct drm_connector *connector, *found = NULL;
115*41ec0267Sriastradh 	struct drm_connector_list_iter iter;
116efa246c0Sriastradh 	struct amdgpu_connector *amdgpu_connector;
117efa246c0Sriastradh 
118*41ec0267Sriastradh 	drm_connector_list_iter_begin(dev, &iter);
119*41ec0267Sriastradh 	drm_for_each_connector_iter(connector, &iter) {
120efa246c0Sriastradh 		amdgpu_connector = to_amdgpu_connector(connector);
121*41ec0267Sriastradh 		if (amdgpu_encoder->devices & amdgpu_connector->devices) {
122*41ec0267Sriastradh 			found = connector;
123*41ec0267Sriastradh 			break;
124efa246c0Sriastradh 		}
125*41ec0267Sriastradh 	}
126*41ec0267Sriastradh 	drm_connector_list_iter_end(&iter);
127*41ec0267Sriastradh 	return found;
128efa246c0Sriastradh }
129efa246c0Sriastradh 
amdgpu_get_external_encoder(struct drm_encoder * encoder)130efa246c0Sriastradh struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder)
131efa246c0Sriastradh {
132efa246c0Sriastradh 	struct drm_device *dev = encoder->dev;
133efa246c0Sriastradh 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
134efa246c0Sriastradh 	struct drm_encoder *other_encoder;
135efa246c0Sriastradh 	struct amdgpu_encoder *other_amdgpu_encoder;
136efa246c0Sriastradh 
137efa246c0Sriastradh 	if (amdgpu_encoder->is_ext_encoder)
138efa246c0Sriastradh 		return NULL;
139efa246c0Sriastradh 
140efa246c0Sriastradh 	list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
141efa246c0Sriastradh 		if (other_encoder == encoder)
142efa246c0Sriastradh 			continue;
143efa246c0Sriastradh 		other_amdgpu_encoder = to_amdgpu_encoder(other_encoder);
144efa246c0Sriastradh 		if (other_amdgpu_encoder->is_ext_encoder &&
145efa246c0Sriastradh 		    (amdgpu_encoder->devices & other_amdgpu_encoder->devices))
146efa246c0Sriastradh 			return other_encoder;
147efa246c0Sriastradh 	}
148efa246c0Sriastradh 	return NULL;
149efa246c0Sriastradh }
150efa246c0Sriastradh 
amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder * encoder)151efa246c0Sriastradh u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
152efa246c0Sriastradh {
153efa246c0Sriastradh 	struct drm_encoder *other_encoder = amdgpu_get_external_encoder(encoder);
154efa246c0Sriastradh 
155efa246c0Sriastradh 	if (other_encoder) {
156efa246c0Sriastradh 		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(other_encoder);
157efa246c0Sriastradh 
158efa246c0Sriastradh 		switch (amdgpu_encoder->encoder_id) {
159efa246c0Sriastradh 		case ENCODER_OBJECT_ID_TRAVIS:
160efa246c0Sriastradh 		case ENCODER_OBJECT_ID_NUTMEG:
161efa246c0Sriastradh 			return amdgpu_encoder->encoder_id;
162efa246c0Sriastradh 		default:
163efa246c0Sriastradh 			return ENCODER_OBJECT_ID_NONE;
164efa246c0Sriastradh 		}
165efa246c0Sriastradh 	}
166efa246c0Sriastradh 	return ENCODER_OBJECT_ID_NONE;
167efa246c0Sriastradh }
168efa246c0Sriastradh 
amdgpu_panel_mode_fixup(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)169efa246c0Sriastradh void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
170efa246c0Sriastradh 			     struct drm_display_mode *adjusted_mode)
171efa246c0Sriastradh {
172efa246c0Sriastradh 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
173efa246c0Sriastradh 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
174efa246c0Sriastradh 	unsigned hblank = native_mode->htotal - native_mode->hdisplay;
175efa246c0Sriastradh 	unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
176efa246c0Sriastradh 	unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
177efa246c0Sriastradh 	unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
178efa246c0Sriastradh 	unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
179efa246c0Sriastradh 	unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
180efa246c0Sriastradh 
181efa246c0Sriastradh 	adjusted_mode->clock = native_mode->clock;
182efa246c0Sriastradh 	adjusted_mode->flags = native_mode->flags;
183efa246c0Sriastradh 
184efa246c0Sriastradh 	adjusted_mode->hdisplay = native_mode->hdisplay;
185efa246c0Sriastradh 	adjusted_mode->vdisplay = native_mode->vdisplay;
186efa246c0Sriastradh 
187efa246c0Sriastradh 	adjusted_mode->htotal = native_mode->hdisplay + hblank;
188efa246c0Sriastradh 	adjusted_mode->hsync_start = native_mode->hdisplay + hover;
189efa246c0Sriastradh 	adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
190efa246c0Sriastradh 
191efa246c0Sriastradh 	adjusted_mode->vtotal = native_mode->vdisplay + vblank;
192efa246c0Sriastradh 	adjusted_mode->vsync_start = native_mode->vdisplay + vover;
193efa246c0Sriastradh 	adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
194efa246c0Sriastradh 
195efa246c0Sriastradh 	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
196efa246c0Sriastradh 
197efa246c0Sriastradh 	adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
198efa246c0Sriastradh 	adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
199efa246c0Sriastradh 
200efa246c0Sriastradh 	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
201efa246c0Sriastradh 	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
202efa246c0Sriastradh 	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
203efa246c0Sriastradh 
204efa246c0Sriastradh 	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
205efa246c0Sriastradh 	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
206efa246c0Sriastradh 	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
207efa246c0Sriastradh 
208efa246c0Sriastradh }
209efa246c0Sriastradh 
amdgpu_dig_monitor_is_duallink(struct drm_encoder * encoder,u32 pixel_clock)210efa246c0Sriastradh bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
211efa246c0Sriastradh 				    u32 pixel_clock)
212efa246c0Sriastradh {
213efa246c0Sriastradh 	struct drm_connector *connector;
214efa246c0Sriastradh 	struct amdgpu_connector *amdgpu_connector;
215efa246c0Sriastradh 	struct amdgpu_connector_atom_dig *dig_connector;
216efa246c0Sriastradh 
217efa246c0Sriastradh 	connector = amdgpu_get_connector_for_encoder(encoder);
218efa246c0Sriastradh 	/* if we don't have an active device yet, just use one of
219efa246c0Sriastradh 	 * the connectors tied to the encoder.
220efa246c0Sriastradh 	 */
221efa246c0Sriastradh 	if (!connector)
222efa246c0Sriastradh 		connector = amdgpu_get_connector_for_encoder_init(encoder);
223efa246c0Sriastradh 	amdgpu_connector = to_amdgpu_connector(connector);
224efa246c0Sriastradh 
225efa246c0Sriastradh 	switch (connector->connector_type) {
226efa246c0Sriastradh 	case DRM_MODE_CONNECTOR_DVII:
227efa246c0Sriastradh 	case DRM_MODE_CONNECTOR_HDMIB:
228efa246c0Sriastradh 		if (amdgpu_connector->use_digital) {
229efa246c0Sriastradh 			/* HDMI 1.3 supports up to 340 Mhz over single link */
230efa246c0Sriastradh 			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
231efa246c0Sriastradh 				if (pixel_clock > 340000)
232efa246c0Sriastradh 					return true;
233efa246c0Sriastradh 				else
234efa246c0Sriastradh 					return false;
235efa246c0Sriastradh 			} else {
236efa246c0Sriastradh 				if (pixel_clock > 165000)
237efa246c0Sriastradh 					return true;
238efa246c0Sriastradh 				else
239efa246c0Sriastradh 					return false;
240efa246c0Sriastradh 			}
241efa246c0Sriastradh 		} else
242efa246c0Sriastradh 			return false;
243efa246c0Sriastradh 	case DRM_MODE_CONNECTOR_DVID:
244efa246c0Sriastradh 	case DRM_MODE_CONNECTOR_HDMIA:
245efa246c0Sriastradh 	case DRM_MODE_CONNECTOR_DisplayPort:
246efa246c0Sriastradh 		dig_connector = amdgpu_connector->con_priv;
247efa246c0Sriastradh 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
248efa246c0Sriastradh 		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
249efa246c0Sriastradh 			return false;
250efa246c0Sriastradh 		else {
251efa246c0Sriastradh 			/* HDMI 1.3 supports up to 340 Mhz over single link */
252efa246c0Sriastradh 			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
253efa246c0Sriastradh 				if (pixel_clock > 340000)
254efa246c0Sriastradh 					return true;
255efa246c0Sriastradh 				else
256efa246c0Sriastradh 					return false;
257efa246c0Sriastradh 			} else {
258efa246c0Sriastradh 				if (pixel_clock > 165000)
259efa246c0Sriastradh 					return true;
260efa246c0Sriastradh 				else
261efa246c0Sriastradh 					return false;
262efa246c0Sriastradh 			}
263efa246c0Sriastradh 		}
264efa246c0Sriastradh 	default:
265efa246c0Sriastradh 		return false;
266efa246c0Sriastradh 	}
267efa246c0Sriastradh }
268