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Searched refs:gpu_offset (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_evergreen_cs.c1178 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1250 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1262 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1274 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1286 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1310 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1330 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1534 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1551 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1592 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
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H A Dradeon_r600_cs.c1026 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1088 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1090 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1109 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1218 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1249 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1285 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1288 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1299 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1301 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()
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H A Dradeon_r200.c196 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
209 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
233 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r200_packet0_check()
235 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
279 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
373 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
H A Dradeon_r300.c708 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
721 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
750 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()
759 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
1120 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
1165 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
1230 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r300_packet3_check()
H A Dradeon_r100.c1299 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()
1350 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1362 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1376 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1617 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1630 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1651 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()
1653 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1671 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1689 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
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H A Dradeon_object.c608 lobj->gpu_offset = radeon_bo_gpu_offset(bo); in radeon_bo_list_validate()
613 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); in radeon_bo_list_validate()
H A Dradeon_cs.c892 (*cs_reloc)->gpu_offset = in radeon_cs_packet_next_reloc()
894 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; in radeon_cs_packet_next_reloc()
H A Dradeon_ttm.c102 man->gpu_offset = rdev->mc.gtt_start; in radeon_init_mem_type()
124 man->gpu_offset = rdev->mc.vram_start; in radeon_init_mem_type()
H A Dradeon_vce.c546 start = reloc->gpu_offset; in radeon_vce_cs_reloc()
H A Dradeon_uvd.c599 start = reloc->gpu_offset; in radeon_uvd_cs_reloc()
H A Dradeon.h480 uint64_t gpu_offset; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/qxl/
H A Dqxl_drv.h139 uint64_t gpu_offset; member
316 WARN_ON_ONCE((bo->tbo.offset & slot->gpu_offset) != slot->gpu_offset); in qxl_bo_physical_address()
319 return slot->high_bits | (bo->tbo.offset - slot->gpu_offset + offset); in qxl_bo_physical_address()
H A Dqxl_ttm.c81 slot->gpu_offset = (uint64_t)type << gpu_offset_shift; in qxl_init_mem_type()
83 man->gpu_offset = slot->gpu_offset; in qxl_init_mem_type()
H A Dqxl_kms.c98 (unsigned long)slot->gpu_offset); in setup_slot()
/netbsd-src/sys/external/bsd/drm2/dist/drm/vmwgfx/
H A Dvmwgfx_ttm_buffer.c763 man->gpu_offset = 0; in vmw_init_mem_type()
776 man->gpu_offset = 0; in vmw_init_mem_type()
/netbsd-src/sys/external/bsd/drm2/dist/include/drm/ttm/
H A Dttm_bo_driver.h182 uint64_t gpu_offset; /* GPU address space is independent of CPU word size */ member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_ttm.c112 man->gpu_offset = adev->gmc.gart_start; in amdgpu_init_mem_type()
120 man->gpu_offset = adev->gmc.vram_start; in amdgpu_init_mem_type()
131 man->gpu_offset = 0; in amdgpu_init_mem_type()
284 addr += bo->bdev->man[mem->mem_type].gpu_offset; in amdgpu_mm_node_addr()
1209 bo->bdev->man[bo->mem.mem_type].gpu_offset; in amdgpu_ttm_alloc_gart()
H A Damdgpu_object.c927 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; in amdgpu_bo_pin_restricted()
/netbsd-src/sys/external/bsd/drm2/dist/drm/ttm/
H A Dttm_bo.c112 drm_printf(p, " gpu_offset: 0x%08"PRIX64"\n", man->gpu_offset); in ttm_mem_type_debug()
412 bdev->man[bo->mem.mem_type].gpu_offset; in ttm_bo_handle_move_mem()