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Searched refs:dev_warn (Results 1 – 25 of 59) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_evergreen_cs.c224 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_linear_aligned()
247 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", in evergreen_surface_check_1d()
255 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", in evergreen_surface_check_1d()
290 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
297 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
323 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_check()
342 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_value_conv_check()
353 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", in evergreen_surface_value_conv_check()
363 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", in evergreen_surface_value_conv_check()
373 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", in evergreen_surface_value_conv_check()
[all …]
H A Dradeon_r600_cs.c370 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", in r600_cs_track_validate_cb()
393 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, in r600_cs_track_validate_cb()
411 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, in r600_cs_track_validate_cb()
418 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_cb()
423 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_cb()
428 dev_warn(p->dev, "%s offset[%d] 0x%"PRIx64" 0x%"PRIx64", %d not aligned\n", __func__, i, in r600_cs_track_validate_cb()
456 dev_warn(p->dev, "%s offset[%d] %d %"PRIu64" %d %lu too big (%d %d) (%d %d %d)\n", in r600_cs_track_validate_cb()
487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large " in r600_cs_track_validate_cb()
505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " in r600_cs_track_validate_cb()
515 dev_warn(p->dev, "%s invalid tile mode\n", __func__); in r600_cs_track_validate_cb()
[all …]
H A Dradeon_device.c493 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); in radeon_wb_init()
505 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); in radeon_wb_init()
512 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); in radeon_wb_init()
598 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); in radeon_vram_location()
604 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); in radeon_vram_location()
636 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
642 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
1230 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", in radeon_check_arguments()
1240 dev_warn(rdev->dev, "gart size (%d) too small\n", in radeon_check_arguments()
1244 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", in radeon_check_arguments()
[all …]
H A Dradeon_r520.c147 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in r520_mc_program()
236 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r520_resume()
281 dev_warn(rdev->dev, in r520_init()
H A Dradeon_agp.c164 dev_warn(rdev->dev, "AGP aperture too small (%zuM) " in radeon_agp_init()
282 dev_warn(rdev->dev, "radeon AGP reinit failed\n"); in radeon_agp_resume()
H A Dradeon_rs400.c407 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); in rs400_mc_program()
481 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs400_resume()
554 dev_warn(rdev->dev, in rs400_init()
H A Dradeon_evergreen.c2873 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2924 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
3927 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_gpu_soft_reset()
4044 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in evergreen_gpu_pci_config_reset()
4123 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); in sumo_rlc_fini()
4135 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); in sumo_rlc_fini()
4147 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r); in sumo_rlc_fini()
4182 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); in sumo_rlc_init()
4196 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); in sumo_rlc_init()
4203 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r); in sumo_rlc_init()
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H A Dradeon_r420.c326 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r420_resume()
416 dev_warn(rdev->dev, in r420_init()
H A Dradeon_rs600.c907 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_gpu_init()
1006 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_mc_program()
1089 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs600_resume()
1163 dev_warn(rdev->dev, in rs600_init()
H A Dradeon_rv770.c1034 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1076 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1617 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1626 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1633 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
H A Dradeon_rs690.c690 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs690_mc_program()
768 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs690_resume()
843 dev_warn(rdev->dev, in rs690_init()
/netbsd-src/sys/external/bsd/drm2/include/linux/
H A Ddevice.h58 #define dev_warn(DEV, FMT, ...) do { \ macro
64 #define dev_WARN dev_warn
92 #define dev_warn_ratelimited dev_warn
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx.c322 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); in amdgpu_gfx_kiq_init_ring()
352 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); in amdgpu_gfx_kiq_init()
360 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); in amdgpu_gfx_kiq_init()
386 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); in amdgpu_gfx_mqd_sw_init()
393 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
405 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); in amdgpu_gfx_mqd_sw_init()
412 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
425 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); in amdgpu_gfx_mqd_sw_init()
432 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
H A Damdgpu_gmc_v6_0.c255 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v6_0_mc_program()
283 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v6_0_mc_program()
444 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); in gmc_v6_0_set_prt()
589 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); in gmc_v6_0_gart_init()
874 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); in gmc_v6_0_sw_init()
1037 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); in gmc_v6_0_soft_reset()
H A Damdgpu_gmc_v7_0.c281 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v7_0_mc_program()
305 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v7_0_mc_program()
565 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); in gmc_v7_0_set_prt()
1220 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); in gmc_v7_0_soft_reset()
H A Damdgpu_gmc_v8_0.c472 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v8_0_mc_program()
507 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v8_0_mc_program()
786 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); in gmc_v8_0_set_prt()
1363 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); in gmc_v8_0_pre_soft_reset()
H A Damdgpu_device.c876 dev_warn(adev->dev, "(%d) create WB bo failed\n", r); in amdgpu_device_wb_init()
1108 dev_warn(adev->dev, "VM page table size (%d) too small\n", in amdgpu_device_check_block_size()
1129 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", in amdgpu_device_check_vm_size()
1186 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", in amdgpu_device_check_arguments()
1190 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", in amdgpu_device_check_arguments()
1197 dev_warn(adev->dev, "gart size (%d) too small\n", in amdgpu_device_check_arguments()
1204 dev_warn(adev->dev, "gtt size (%d) too small\n", in amdgpu_device_check_arguments()
1212 dev_warn(adev->dev, "valid range is between 4 and 9\n"); in amdgpu_device_check_arguments()
H A Damdgpu_si_ih.c119 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in si_ih_get_wptr()
H A Damdgpu_rlc.c106 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); in amdgpu_gfx_rlc_init_sr()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
H A Dintel_uc_fw.c298 dev_warn(dev, "%s firmware %s: invalid size: %zu < %zu\n", in intel_uc_fw_fetch()
311 dev_warn(dev, in intel_uc_fw_fetch()
324 dev_warn(dev, "%s firmware %s: unexpected key size: %u != %u\n", in intel_uc_fw_fetch()
335 dev_warn(dev, "%s firmware %s: invalid size: %zu < %zu\n", in intel_uc_fw_fetch()
345 dev_warn(dev, "%s firmware %s: invalid size: %zu > %zu\n", in intel_uc_fw_fetch()
/netbsd-src/sys/external/bsd/dwc2/
H A Ddwc2.h79 #define dev_warn(d,fmt,...) do { \ macro
101 #define dev_warn(...) do { } while (0) macro
/netbsd-src/sys/external/bsd/dwc2/dist/
H A Ddwc2_coreintr.c115 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", in dwc2_handle_mode_mismatch_intr()
545 dev_warn(hsotg->dev, "Controller is dead\n"); in dwc2_handle_common_intr()
H A Ddwc2_hcdintr.c491 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); in dwc2_update_urb_state()
1205 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); in dwc2_update_urb_state_abn()
1810 dev_warn(hsotg->dev, in dwc2_halt_status_ok()
1823 dev_warn(hsotg->dev, in dwc2_halt_status_ok()
2209 dev_warn(hsotg->dev, "Controller is dead\n"); in dwc2_handle_hcd_intr()
H A Ddwc2_core.c509 dev_warn(hsotg->dev, in dwc2_core_reset()
522 dev_warn(hsotg->dev, in dwc2_core_reset()
632 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", in dwc2_force_dr_mode()
2016 dev_warn(hsotg->dev, in dwc2_hc_start_transfer()
2111 dev_warn(hsotg->dev, in dwc2_hc_start_transfer_ddma()
2504 dev_warn(hsotg->dev, in dwc2_flush_tx_fifo()
2535 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", in dwc2_flush_rx_fifo()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_common_baco.c80 dev_warn(adev->dev, "Invalid BACO command.\n"); in baco_cmd_handler()

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