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/netbsd-src/sys/arch/arm/nxp/
H A Dimx6_ccmvar.h195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \ argument
203 .mask = (CCM_ANALOG_##_reg##_##_mask), \
210 #define CLK_DIV(_name, _parent, _reg, _mask) { \ argument
219 .mask = (CCM_##_reg##_##_mask), \
224 #define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \ argument
233 .mask = (CCM_##_reg##_##_mask), \
240 #define CLK_DIV_TABLE(_name, _parent, _reg, _mask, _tbl) { \ argument
249 .mask = (CCM_ANALOG_##_reg##_##_mask), \
255 #define CLK_MUX(_name, _parents, _base, _reg, _mask) { \ argument
263 .mask = (_base##_##_reg##_##_mask), \
[all …]
H A Dimx_ccm.h87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \ argument
88 IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)
89 #define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \ argument
98 .u.gate.mask = (_mask), \
268 #define IMX_DIV(_id, _name, _parent, _reg, _mask, _flags) \ argument
269 IMX_DIV_INDEX(_id, 0, _name, _parent, _reg, _mask, _flags)
270 #define IMX_DIV_INDEX(_id, _regidx, _name, _parent, _reg, _mask, _flags) \ argument
279 .u.div.mask = (_mask), \
H A Dimx7d_ccm.c101 #define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \ argument
102 IMX_MUX_INDEX(_id, REGIDX_ANATOP, _name, _parents, _reg, _mask)
103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \ argument
104 IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)
/netbsd-src/external/lgpl3/mpfr/dist/src/
H A Dmpfr-gmp.h481 mp_limb_t _q0, _t1, _t0, _mask; \
494 _mask = - (mp_limb_t) ((r1) >= _q0); \
495 (q) += _mask; \
496 add_ssaaaa ((r1), (r0), (r1), (r0), _mask & (d1), _mask & (d0)); \
516 mp_limb_t _v, _p, _t1, _t0, _mask; \
523 _mask = -(mp_limb_t) (_p >= (d1)); \
525 _v += _mask; \
526 _p -= _mask & (d1); \
549 mp_limb_t _qh, _ql, _r, _mask; \
555 _mask = -(mp_limb_t) (_r > _ql); /* both > and >= are OK */ \
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td779 def "int_riscv_" # NAME # "_mask" : RISCVUSLoadMask;
783 def "int_riscv_" # NAME # "_mask" : RISCVUSLoadFFMask;
787 def "int_riscv_" # NAME # "_mask" : RISCVSLoadMask;
791 def "int_riscv_" # NAME # "_mask" : RISCVILoadMask;
795 def "int_riscv_" # NAME # "_mask" : RISCVUSStoreMask;
799 def "int_riscv_" # NAME # "_mask" : RISCVSStoreMask;
804 def "int_riscv_" # NAME # "_mask" : RISCVIStoreMask;
808 def "int_riscv_" # NAME # "_mask" : RISCVUnaryAAMask;
812 def "int_riscv_" # NAME # "_mask" : RISCVUnaryABMask;
818 def "int_riscv_" # NAME # "_mask" : RISCVBinaryAAXMask;
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/netbsd-src/sys/external/mit/xen-include-public/dist/xen/include/public/io/
H A Dring.h384 static inline RING_IDX name##_mask(RING_IDX idx, RING_IDX ring_size) \
393 return buf + name##_mask(idx, ring_size); \
411 *masked_cons = name##_mask(*masked_cons + size, ring_size); \
429 *masked_prod = name##_mask(*masked_prod + size, ring_size); \
441 prod = name##_mask(prod, ring_size); \
442 cons = name##_mask(cons, ring_size); \
/netbsd-src/sys/arch/powerpc/marvell/
H A Dpic_discovery.c64 } _mask; member
65 #define enable_mask _mask.mask64
66 #define enable_mask_high _mask.mask32[1]
67 #define enable_mask_low _mask.mask32[0]
/netbsd-src/external/lgpl3/gmp/dist/mpn/generic/
H A Ddiv_qr_2.c119 mp_limb_t _mask; \
137 _mask = -(mp_limb_t) ((r1 >= _q1) & ((r1 > _q1) | (r0 >= _q0))); /* (r1,r0) >= (q1,q0) */ \
138 add_ssaaaa (r1, r0, r1, r0, d1 & _mask, d0 & _mask); \
139 sub_ddmmss (_q3, _q2, _q3, _q2, CNST_LIMB(0), -_mask); \
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
H A Dddc_regs.h38 ….type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MAS…
61 .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
78 .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
H A Dgeneric_regs.h35 .type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\
H A Dhpd_regs.h43 .type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\
H A Damdgpu_hw_gpio.c40 gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
/netbsd-src/sys/arch/arm/rockchip/
H A Drk_cru.h391 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \ argument
400 .u.mux.mask = (_mask), \
405 #define RK_MUX(_id, _name, _parents, _reg, _mask) \ argument
406 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0)
407 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \ argument
408 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, RK_MUX_GRF)
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Dsubst.md47 (define_subst_attr "mask_name" "mask" "" "_mask")
48 (define_subst_attr "maskc_name" "maskc" "" "_mask")
114 (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
322 (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
338 (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
340 (define_subst_attr "mask_scalarc_name" "mask_scalarc" "" "_mask")
H A Dsse.md1335 (define_expand "<avx512>_load<mode>_mask"
1354 (define_insn "*<avx512>_load<mode>_mask"
1393 (define_expand "<avx512>_load<mode>_mask"
1413 (define_insn "*<avx512>_load<mode>_mask"
1437 (define_insn "avx512f_mov<ssescalarmodelower>_mask"
1452 (define_expand "avx512f_load<mode>_mask"
1465 (define_insn "*avx512f_load<mode>_mask"
1482 (define_insn "avx512f_store<mode>_mask"
1557 (define_insn "*<avx512>_store<mode>_mask"
1585 (define_insn "*<avx512>_store<mode>_mask"
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/netbsd-src/sys/arch/arm/ti/
H A Dti_prcm.h146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \ argument
150 .u.hwmod.mask = (_mask), \
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Dsubst.md42 (define_subst_attr "mask_name" "mask" "" "_mask")
78 (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
233 (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
249 (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
/netbsd-src/external/lgpl3/gmp/dist/
H A Dgmp-impl.h3070 mp_limb_t _v, _p, _t1, _t0, _mask; \
3077 _mask = -(mp_limb_t) (_p >= (d1)); \
3079 _v += _mask; \
3080 _p -= _mask & (d1); \
3120 mp_limb_t _qh, _ql, _r, _mask; \
3126 _mask = -(mp_limb_t) (_r > _ql); /* both > and >= are OK */ \
3127 _qh += _mask; \
3128 _r += _mask & (d); \
3134 _mask = -(mp_limb_t) (_r > _ql); /* both > and >= are OK */ \
3135 _qh += _mask; \
[all …]
/netbsd-src/external/bsd/wpa/dist/src/eap_common/
H A Deap_pwd_common.h74 struct crypto_bignum *_mask,
/netbsd-src/sys/arch/arm/amlogic/
H A Dmeson_clk.h237 #define MESON_CLK_PLL_REG(_reg, _mask) \ argument
238 { .reg = (_reg), .mask = (_mask) }
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/Basic/
H A Driscv_vector.td197 string IRNameMask = NAME #"_mask";
235 let IRName = intrinsic_name, IRNameMask = intrinsic_name # "_mask",
350 let IRNameMask = intrinsic_name # "_mask";
485 IRName = intrinsic_name, IRNameMask = intrinsic_name # "_mask" in {
501 IRName = intrinsic_name, IRNameMask = intrinsic_name # "_mask" in {
673 let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
760 let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
780 IRNameMask = NAME # "_mask",
803 IRNameMask = IR # "_mask",
832 IRNameMask = IR # "_mask",
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/netbsd-src/external/bsd/file/dist/src/
H A Dfile.h359 uint64_t _mask; /* for use with numeric and date types */ member
365 #define num_mask _u._mask
/netbsd-src/sys/arch/arm/sunxi/
H A Dsunxi_ccu.h326 #define SUNXI_CCU_PHASE(_id, _name, _parent, _reg, _mask) \ argument
332 .u.phase.mask = (_mask), \
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/tilepro/
H A Datomic.h191 #define __arch_atomic_update(mem, value, op, _mask, _addend, _expr) \ argument
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/tilepro/
H A Datomic.h191 #define __arch_atomic_update(mem, value, op, _mask, _addend, _expr) \ argument

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