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Searched refs:WREG32_SMC (Results 1 – 21 of 21) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_trinity_smc.c71 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config()
73 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config()
80 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state()
87 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
H A Dradeon_trinity_dpm.c388 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize()
512 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()
530 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
535 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
539 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
543 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
604 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()
614 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); in trinity_set_divider_value()
626 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()
638 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers()
[all …]
H A Dradeon_ci_smc.c124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
132 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
148 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock()
157 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
H A Dradeon_si_smc.c124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
138 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
154 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock()
163 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
H A Dradeon_ci_dpm.c604 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
894 WREG32_SMC(CG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
901 WREG32_SMC(CG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
918 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
927 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
954 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
958 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1132 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
1209 WREG32_SMC(CG_TACH_CTRL, tmp);
1225 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
[all …]
H A Dradeon_kv_dpm.c281 WREG32_SMC(local_cac_reg->cntl, data);
321 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
412 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
413 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
416 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
417 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
420 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
421 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
424 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
425 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
[all …]
H A Dradeon_cik.c9505 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
9552 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
9851 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm()
9857 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm()
9862 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm()
9867 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm()
9873 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
H A Dradeon_si.c5473 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5474 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5485 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5486 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
H A Dradeon.h2608 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro
2642 WREG32_SMC(reg, tmp_); \
H A Dradeon_si_dpm.c2770 WREG32_SMC(offset, data); in si_program_cac_config_registers()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_si_smc.c122 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_start_smc()
136 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_reset_smc()
155 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_si_smc_clock()
H A Damdgpu_kv_dpm.c408 WREG32_SMC(local_cac_reg->cntl, data);
448 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
539 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
540 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
543 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
544 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
547 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
548 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
551 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
552 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
[all …]
H A Damdgpu_cik.c928 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios()
939 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios()
1400 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
1449 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
1760 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm()
1768 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm()
1773 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
1778 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
1784 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
H A Damdgpu_vi.c412 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios()
423 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios()
811 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock()
901 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks()
1507 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); in vi_update_rom_medium_grain_clock_gating()
H A Damdgpu_cgs.c103 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
H A Damdgpu_debugfs.c517 WREG32_SMC(*pos, value); in amdgpu_debugfs_regs_smc_write()
H A Damdgpu.h1065 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro
H A Damdgpu_vce_v4_0.c890 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
H A Damdgpu_si_dpm.c2870 WREG32_SMC(offset, data); in si_program_cac_config_registers()
7524 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7529 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7541 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7546 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
H A Damdgpu_uvd_v7_0.c1696 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
H A Damdgpu_gfx_v8_0.c801 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); in gfx_v8_0_init_golden_registers()