Searched refs:SCI_CSR_PHASE_MATCH (Results 1 – 11 of 11) sorted by relevance
223 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in wstsc_dma_xfer_in()224 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in wstsc_dma_xfer_in()225 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in wstsc_dma_xfer_in()260 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in wstsc_dma_xfer_in()261 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in wstsc_dma_xfer_in()262 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in wstsc_dma_xfer_in()307 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in wstsc_dma_xfer_out()308 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in wstsc_dma_xfer_out()309 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in wstsc_dma_xfer_out()327 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == in wstsc_dma_xfer_out()[all …]
201 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in mlhsc_dma_xfer_in()202 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in mlhsc_dma_xfer_in()203 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in mlhsc_dma_xfer_in()237 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in mlhsc_dma_xfer_in()238 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in mlhsc_dma_xfer_in()239 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in mlhsc_dma_xfer_in()288 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in mlhsc_dma_xfer_out()289 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in mlhsc_dma_xfer_out()290 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in mlhsc_dma_xfer_out()316 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in mlhsc_dma_xfer_out()[all …]
211 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in ivsc_dma_xfer_in()212 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in ivsc_dma_xfer_in()213 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in ivsc_dma_xfer_in()248 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in ivsc_dma_xfer_in()249 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in ivsc_dma_xfer_in()250 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in ivsc_dma_xfer_in()295 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in ivsc_dma_xfer_out()296 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in ivsc_dma_xfer_out()297 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in ivsc_dma_xfer_out()315 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == in ivsc_dma_xfer_out()[all …]
204 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in otgsc_dma_xfer_in()205 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in otgsc_dma_xfer_in()206 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in otgsc_dma_xfer_in()251 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != in otgsc_dma_xfer_out()252 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in otgsc_dma_xfer_out()253 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) in otgsc_dma_xfer_out()271 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == in otgsc_dma_xfer_out()272 SCI_CSR_PHASE_MATCH && --wait); in otgsc_dma_xfer_out()
141 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */ macro
432 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH)) in sci_ixfer_out()479 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH)) in sci_ixfer_in()
135 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) in sbc_ready() 136 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in sbc_ready() 140 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0) in sbc_ready() 158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) in sbc_wait_dreq() 159 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { in sbc_wait_dreq() 186 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) in sbc_irq_intr() 210 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) && in decode_5380_intr() 219 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) && in decode_5380_intr() 222 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) && in decode_5380_intr() 228 else if (((csr & ~SCI_CSR_PHASE_MATCH) in decode_5380_intr() [all...]
233 if ((status & (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) ==234 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH))237 if ((status & SCI_CSR_PHASE_MATCH) == 0 ||271 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||376 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
235 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == in hcsc_ready()236 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) in hcsc_ready()239 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || in hcsc_ready()256 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || in hcsc_wait_not_req()356 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) in hcsc_pdma_out()
137 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */ macro
156 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */ macro