223 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=  in wstsc_dma_xfer_in()
224 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {  in wstsc_dma_xfer_in()
225 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)  in wstsc_dma_xfer_in()
260 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=  in wstsc_dma_xfer_in()
261 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {  in wstsc_dma_xfer_in()
262 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)  in wstsc_dma_xfer_in()
307 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=  in wstsc_dma_xfer_out()
308 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {  in wstsc_dma_xfer_out()
309 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)  in wstsc_dma_xfer_out()
327 	while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==  in wstsc_dma_xfer_out()
328 	  SCI_CSR_PHASE_MATCH && --wait);  in wstsc_dma_xfer_out()
360 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=  in wstsc_dma_xfer_in2()
361 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {  in wstsc_dma_xfer_in2()
362 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)  in wstsc_dma_xfer_in2()
393 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=  in wstsc_dma_xfer_in2()
394 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {  in wstsc_dma_xfer_in2()
395 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)  in wstsc_dma_xfer_in2()
452 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=  in wstsc_dma_xfer_out2()
453 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {  in wstsc_dma_xfer_out2()
454 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)  in wstsc_dma_xfer_out2()
486 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=  in wstsc_dma_xfer_out2()
487 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {  in wstsc_dma_xfer_out2()
488 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)  in wstsc_dma_xfer_out2()
517 	while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==  in wstsc_dma_xfer_out2()
518 	  SCI_CSR_PHASE_MATCH && --wait);  in wstsc_dma_xfer_out2()