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Searched refs:SAHF (Results 1 – 16 of 16) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DX86TargetParser.def178 X86_FEATURE (SAHF, "sahf")
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Dx86-tune.def281 /* X86_TUNE_USE_SAHF: Controls use of SAHF. */
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Dx86-tune.def309 /* X86_TUNE_USE_SAHF: Controls use of SAHF. */
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5395 SDValue SAHF = SDValue( in Select() local
5396 CurDAG->getMachineNode(X86::SAHF, dl, MVT::i32, AH.getValue(1)), 0); in Select()
5401 ReplaceUses(SDValue(Node, 0), SAHF); in Select()
H A DX86ScheduleBdVer2.td525 def : InstRW<[PdWriteSAHF], (instrs SAHF)>;
H A DX86.td241 "Support LAHF and SAHF instructions in 64-bit mode">;
H A DX86InstrInfo.td1867 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, // flags = AH
/netbsd-src/external/gpl3/gcc/dist/gcc/doc/
H A Dinvoke.texi31451 SAHF and FXSR instruction set support.
31455 SSE4.1, SSE4.2, POPCNT, CX16, SAHF and FXSR instruction set support.
31459 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR and PCLMUL instruction set support.
31463 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE and PCLMUL instruction set
31468 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND
31473 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
31478 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
31484 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
31494 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW and RDRND
31499 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW, RDRND, AES, SHA,
[all …]
H A Dgcc.info28657 SSSE3, CX16, SAHF and FXSR instruction set support.
28661 SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF and FXSR
28666 SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR and
28671 SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX,
28676 SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX,
28682 SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR,
28688 SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR,
28695 SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR,
28706 SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR,
28711 SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR,
[all …]
H A Dextend.texi6893 Enable/disable the generation of the SAHF instructions.
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DCodeGenerator.rst403 MI = BuildMI(MBB, DL, TII.get(X86::SAHF));
/netbsd-src/external/apache2/llvm/dist/clang/docs/
H A DUsersManual.rst3327 - ``-march=x86-64-v2``: (close to Nehalem) CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSS…
/netbsd-src/external/gpl3/gcc.old/dist/gcc/doc/
H A Dinvoke.texi29728 This option enables generation of @code{SAHF} instructions in 64-bit code.
29731 lacked the @code{LAHF} and @code{SAHF} instructions
29734 In 64-bit mode, the @code{SAHF} instruction is used to optimize @code{fmod},
H A Dgcc.info27044 This option enables generation of 'SAHF' instructions in 64-bit
27047 'LAHF' and 'SAHF' instructions which are supported by AMD64. These
27049 flags. In 64-bit mode, the 'SAHF' instruction is used to optimize
34971 Enable/disable the generation of the SAHF instructions.
H A Dextend.texi6507 Enable/disable the generation of the SAHF instructions.
/netbsd-src/external/gpl3/binutils/dist/
H A DChangeLog.git67543 x86-64: don't permit LAHF/SAHF with "generic64"