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Searched refs:PCLK (Results 1 – 25 of 42) sorted by relevance

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/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dgemini.dtsi165 clock-names = "PCLK";
189 clock-names = "PCLK", "EXTCLK";
199 clock-names = "PCLK", "EXTCLK";
286 clock-names = "PCLK", "PCICLK";
345 clock-names = "PCLK";
356 clock-names = "PCLK";
374 clock-names = "PCLK";
387 clock-names = "PCLK";
418 clock-names = "PCLK", "TVE";
430 clock-names = "PCLK";
[all …]
H A Dmoxart.dtsi65 clock-names = "PCLK";
93 clock-names = "PCLK";
/netbsd-src/sys/arch/ews4800mips/sbd/
H A Dzs_sbdio.c58 #define PCLK (9600 * 512) /* 4.915200MHz */ macro
87 BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /* 12: BAUDLO (default=9600) */
156 cs->cs_brg_clk = PCLK / 16; in zs_sbdio_attach()
250 cs->cs_brg_clk = PCLK / 16; in zs_sbdio_cninit()
/netbsd-src/sys/arch/mac68k/dev/
H A Dzs.c85 #define PCLK (9600 * 384) macro
164 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
276 cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */ in zsc_attach()
291 xcs->cs_clocks[0].clk = PCLK; in zsc_attach()
478 tc = BPS_TO_TCONST(PCLK / 16, bps); in zs_cn_check_speed()
481 rate = TCONST_TO_BPS(PCLK / 16, tc); in zs_cn_check_speed()
593 cs->cs_brg_clk = PCLK / 16; in zs_set_speed()
828 cs->cs_brg_clk = PCLK / 16; in zscnsetup()
H A Dzs_kgdb.c66 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ macro
167 cs.cs_brg_clk = PCLK / 16; in zs_kgdb_init()
/netbsd-src/sys/arch/next68k/dev/
H A Dzs_kgdb.c67 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ macro
93 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
157 cs.cs_brg_clk = PCLK / 16; in zs_kgdb_init()
H A Dzs.c96 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ macro
130 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
224 cs->cs_brg_clk = PCLK / 16; in zs_attach()
622 cs->cs_brg_clk = PCLK / 16; in zscninit()
/netbsd-src/sys/arch/cobalt/dev/
H A Dzs.c72 #define PCLK (115200 * 96) /* 11.0592MHz */ macro
122 BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /*12: BAUDLO */
202 cs->cs_brg_clk = PCLK / 16; in zs_attach()
527 cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED); in zscninit()
/netbsd-src/sys/arch/x68k/dev/
H A Dzs.c87 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */ macro
113 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
210 cs->cs_brg_clk = PCLK / 16; in zs_attach()
584 zscn_cs.cs_brg_clk = PCLK / 16; in zscninit()
/netbsd-src/sys/arch/newsmips/dev/
H A Dzs_hb.c75 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ macro
119 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
235 cs->cs_brg_clk = PCLK / 16; in zs_hb_attach()
/netbsd-src/sys/arch/newsmips/apbus/
H A Dzs_ap.c127 #define PCLK (9600 * 1024) /* PCLK pin input clock rate */ macro
162 BPS_TO_TCONST(PCLK/16,9600), /*12: BAUDLO (default=9600) */
346 cs->cs_brg_clk = PCLK / 16; in zs_ap_attach()
562 cs->cs_brg_clk = PCLK / 16; in zscninit()
/netbsd-src/sys/arch/sun3/dev/
H A Dzs_kgdb.c63 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ macro
158 cs.cs_brg_clk = PCLK / 16; in zs_kgdb_init()
H A Dzs.c97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ macro
153 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
286 cs->cs_brg_clk = PCLK / 16; in zs_attach()
/netbsd-src/sys/arch/macppc/dev/
H A Dzs_kgdb.c78 ((PCLK/32)/38400)-2, /*12: BAUDLO (default=38400) */
165 cs.cs_brg_clk = PCLK / 16; in zs_kgdb_init()
H A Dzs.c162 ((PCLK/32)/38400)-2, /*12: BAUDLO (default=38400) */
303 cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */ in zsc_attach()
321 xcs->cs_clocks[0].clk = PCLK; in zsc_attach()
657 cs->cs_brg_clk = PCLK / 16; in zs_set_speed()
/netbsd-src/sys/arch/sparc/dev/
H A Dzs_kgdb.c65 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ macro
165 cs.cs_brg_clk = PCLK / 16; in zs_kgdb_init()
/netbsd-src/sys/arch/atari/dev/
H A Dzs.c116 #define PCLK (8053976) /* PCLK pin input clock rate */ macro
166 PCLK/16, /* BRgen, PCLK, divisor 16 */
171 PCLK/16, /* BRgen, PCLK, divisor 16 */
181 PCLK/16, /* BRgen, PCLK, divisor 16 */
186 PCLK/16, /* BRgen, PCLK, divisor 16 */
211 PCLK/16, /* BRgen, PCLK, divisor 16 */
216 PCLK/16, /* BRgen, PCLK, divisor 16 */
/netbsd-src/sys/arch/sun2/dev/
H A Dzsreg.h35 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ macro
/netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Ds3c2410.h28 #define PCLK 6 macro
H A Ds3c2412.h30 #define PCLK 8 macro
H A Ds3c2443.h27 #define PCLK 6 macro
/netbsd-src/sys/arch/mipsco/obio/
H A Dzs.c85 #define PCLK 10000000 /* PCLK pin input clock rate */ macro
142 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */
232 cs->cs_brg_clk = PCLK / 16; in zs_attach()
/netbsd-src/sys/arch/sgimips/dev/
H A Dzs.c81 #define PCLK 3672000 /* PCLK pin input clock rate */ macro
162 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */
254 cs->cs_brg_clk = PCLK / 16; in zs_hpc_attach()
/netbsd-src/sys/dev/tc/
H A Dzs_ioasic.c112 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ macro
268 cs->cs_brg_clk = PCLK / 16; in zs_ioasic_attach()
735 cs->cs_brg_clk = PCLK / 16; in zs_ioasic_cninit()
/netbsd-src/sys/arch/sparc64/dev/
H A Dzs.c98 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ macro
134 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
361 cs->cs_brg_clk = PCLK / 16; in zs_attach()

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