Home
last modified time | relevance | path

Searched refs:I915_READ (Results 1 – 25 of 46) sorted by relevance

12

/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Di915_suspend.c40 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); in i915_pipe_enabled()
42 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); in i915_pipe_enabled()
61 array[i] = I915_READ(reg + (i << 2)); in i915_save_palette()
253 dev_priv->saveDSPARB = I915_READ(DSPARB); in i915_save_state()
256 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); in i915_save_state()
257 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); in i915_save_state()
258 dev_priv->saveFPA0 = I915_READ(FPA0); in i915_save_state()
259 dev_priv->saveFPA1 = I915_READ(FPA1); in i915_save_state()
260 dev_priv->saveDPLL_A = I915_READ(DPLL_A); in i915_save_state()
262 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); in i915_save_state()
[all …]
H A Di915_irq.c62 (void) I915_READ(IMR); in i915_enable_irq()
73 (void) I915_READ(IMR); in i915_disable_irq()
96 (void) I915_READ(reg); in i915_enable_pipestat()
108 (void) I915_READ(reg); in i915_disable_pipestat()
127 if (I915_READ(pipeconf) & PIPEACONF_ENABLE) in i915_pipe_enabled()
157 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> in i915_get_vblank_counter()
159 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> in i915_get_vblank_counter()
161 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> in i915_get_vblank_counter()
180 return I915_READ(reg); in gm45_get_vblank_counter()
192 iir = I915_READ(IIR); in i915_driver_irq_handler()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_combo_phy.c56 val = I915_READ(ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
89 val = I915_READ(ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
102 u32 val = I915_READ(reg); in check_phy_reg()
135 return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && in cnl_combo_phy_enabled()
136 (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT); in cnl_combo_phy_enabled()
159 val = I915_READ(CHICKEN_MISC_2); in cnl_combo_phys_init()
166 val = I915_READ(CNL_PORT_COMP_DW0); in cnl_combo_phys_init()
170 val = I915_READ(CNL_PORT_CL1CM_DW5); in cnl_combo_phys_init()
182 val = I915_READ(CHICKEN_MISC_2); in cnl_combo_phys_uninit()
192 return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
[all …]
H A Dintel_dpll_mgr.c388 val = I915_READ(PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
390 hw_state->fp0 = I915_READ(PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
391 hw_state->fp1 = I915_READ(PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
414 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
533 val = I915_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
551 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_disable()
576 val = I915_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
596 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_get_hw_state()
999 val = I915_READ(DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1025 I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
[all …]
H A Dicl_dsi.c47 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
54 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
117 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) & in wait_for_cmds_dispatched_to_panel()
166 tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
220 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); in dsi_program_swing_and_deemphasis()
227 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); in dsi_program_swing_and_deemphasis()
234 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); in dsi_program_swing_and_deemphasis()
242 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); in dsi_program_swing_and_deemphasis()
250 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); in dsi_program_swing_and_deemphasis()
260 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); in dsi_program_swing_and_deemphasis()
[all …]
H A Dvlv_dsi.c119 u32 val = I915_READ(reg); in read_data()
234 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
336 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
341 tmp = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
347 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
348 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
365 !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
386 val = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
391 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
392 val = I915_READ(MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
[all …]
H A Dintel_audio.c299 tmp = I915_READ(reg_eldv); in intel_eld_uptodate()
305 tmp = I915_READ(reg_elda); in intel_eld_uptodate()
310 if (I915_READ(reg_edid) != *((const u32 *)eld + i)) in intel_eld_uptodate()
325 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_disable()
332 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
350 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_enable()
362 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
372 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
396 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); in hsw_dp_audio_config_update()
410 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); in hsw_dp_audio_config_update()
[all …]
H A Dintel_ddi.c826 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_hdmi()
847 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_dp()
868 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_edp()
1041 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
1187 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1195 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
1214 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1220 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1229 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1282 wrpll = I915_READ(reg); in hsw_ddi_calc_wrpll_link()
[all …]
H A Dintel_panel.c549 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
556 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
565 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
584 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in _vlv_get_backlight()
600 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); in bxt_get_backlight()
619 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
629 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
657 tmp = I915_READ(BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
668 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
760 tmp = I915_READ(BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
H A Dintel_display_power.c316 ret = I915_READ(regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
317 ret |= I915_READ(regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
319 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
320 ret |= I915_READ(regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
342 wait_for((disabled = !(I915_READ(regs->driver) & in hsw_wait_for_power_well_disable()
384 val = I915_READ(regs->driver); in hsw_power_well_enable()
392 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx)); in hsw_power_well_enable()
415 val = I915_READ(regs->driver); in hsw_power_well_disable()
433 val = I915_READ(regs->driver); in icl_combo_phy_aux_power_well_enable()
437 val = I915_READ(ICL_PORT_CL_DW12(phy)); in icl_combo_phy_aux_power_well_enable()
[all …]
H A Dintel_dpio_phy.c286 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
290 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
295 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
305 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
310 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
322 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
325 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
333 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
345 u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
381 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
[all …]
H A Dintel_cdclk.c245 tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? in intel_hpll_vco()
415 u32 lcpll = I915_READ(LCPLL_CTL); in hsw_get_cdclk()
420 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
528 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
695 u32 lcpll = I915_READ(LCPLL_CTL); in bdw_get_cdclk()
700 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
727 if (WARN((I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
742 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
750 if (wait_for_us(I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
754 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
[all …]
H A Dvlv_dsi_pll.c209 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
223 val = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
246 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
333 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
351 temp = I915_READ(MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
420 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
530 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
552 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
559 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
563 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
H A Dintel_display.c531 I915_READ(CLKGATE_DIS_PSL(pipe)) | in skl_wa_827()
535 I915_READ(CLKGATE_DIS_PSL(pipe)) & in skl_wa_827()
546 I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); in icl_wa_scalerclkgating()
549 I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); in icl_wa_scalerclkgating()
1061 line1 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1063 line2 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1115 val = I915_READ(DPLL(pipe)); in assert_pll()
1151 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1154 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1170 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
[all …]
H A Dintel_lvds.c93 val = I915_READ(lvds_reg); in intel_lvds_port_enabled()
133 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_config()
151 tmp = I915_READ(PFIT_CONTROL); in intel_lvds_get_config()
164 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
166 val = I915_READ(PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
171 val = I915_READ(PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
175 val = I915_READ(PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
211 val = I915_READ(PP_CONTROL(0)); in intel_lvds_pps_init_hw()
321 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
323 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
[all …]
H A Dintel_dvo.c145 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
160 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
176 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
198 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
202 I915_READ(dvo_reg); in intel_disable_dvo()
212 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
219 I915_READ(dvo_reg); in intel_enable_dvo()
294 dvo_val = I915_READ(dvo_reg) & in intel_dvo_pre_enable()
489 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
H A Dintel_fifo_underrun.c103 if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
129 if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
151 u32 err_int = I915_READ(GEN7_ERR_INT); in ivb_check_fifo_underruns()
181 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
217 u32 serr_int = I915_READ(SERR_INT); in cpt_check_pch_fifo_underruns()
249 if (old && I915_READ(SERR_INT) & in cpt_set_fifo_underrun_reporting()
H A Dintel_hdmi.c80 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
88 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
223 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
260 val = I915_READ(VIDEO_DIP_CTL); in g4x_read_infoframe()
268 *data++ = I915_READ(VIDEO_DIP_DATA); in g4x_read_infoframe()
275 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_infoframes_enabled()
296 u32 val = I915_READ(reg); in ibx_write_infoframe()
334 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); in ibx_read_infoframe()
342 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
351 u32 val = I915_READ(reg); in ibx_infoframes_enabled()
[all …]
H A Dintel_crt.c83 val = I915_READ(adpa_reg); in intel_crt_port_enabled()
120 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_flags()
450 save_adpa = adpa = I915_READ(crt->adpa_reg); in ilk_crt_detect_hotplug()
472 adpa = I915_READ(crt->adpa_reg); in ilk_crt_detect_hotplug()
506 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
520 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
569 stat = I915_READ(PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
714 u32 vsync = I915_READ(vsync_reg); in intel_crt_load_detect()
926 adpa = I915_READ(crt->adpa_reg); in intel_crt_reset()
977 adpa = I915_READ(adpa_reg); in intel_crt_init()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_suspend.c46 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
50 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
82 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
85 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); in i915_save_state()
90 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
91 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
94 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); in i915_save_state()
97 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
100 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
101 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
[all …]
H A Di915_debugfs.c410 I915_READ(GEN8_DE_PIPE_IMR(pipe))); in gen8_display_interrupt_info()
413 I915_READ(GEN8_DE_PIPE_IIR(pipe))); in gen8_display_interrupt_info()
416 I915_READ(GEN8_DE_PIPE_IER(pipe))); in gen8_display_interrupt_info()
422 I915_READ(GEN8_DE_PORT_IMR)); in gen8_display_interrupt_info()
424 I915_READ(GEN8_DE_PORT_IIR)); in gen8_display_interrupt_info()
426 I915_READ(GEN8_DE_PORT_IER)); in gen8_display_interrupt_info()
429 I915_READ(GEN8_DE_MISC_IMR)); in gen8_display_interrupt_info()
431 I915_READ(GEN8_DE_MISC_IIR)); in gen8_display_interrupt_info()
433 I915_READ(GEN8_DE_MISC_IER)); in gen8_display_interrupt_info()
436 I915_READ(GEN8_PCU_IMR)); in gen8_display_interrupt_info()
[all …]
H A Di915_drv.c853 val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); in skl_dram_get_channels_info()
858 val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); in skl_dram_get_channels_info()
897 val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); in skl_get_dram_type()
928 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); in skl_get_dram_info()
1032 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0); in bxt_get_dram_info()
1054 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i)); in bxt_get_dram_info()
2248 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
2249 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
2250 s->arb_mode = I915_READ(ARB_MODE); in vlv_save_gunit_s0ix_state()
2251 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
[all …]
H A Dintel_device_info.c252 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; in gen12_sseu_info_init()
254 dss_en = I915_READ(GEN12_GT_DSS_ENABLE); in gen12_sseu_info_init()
257 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); in gen12_sseu_info_init()
280 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; in gen11_sseu_info_init()
281 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); in gen11_sseu_info_init()
282 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); in gen11_sseu_info_init()
295 const u32 fuse2 = I915_READ(GEN8_FUSE2); in gen10_sseu_info_init()
306 eu_en = ~I915_READ(GEN8_EU_DISABLE0); in gen10_sseu_info_init()
311 eu_en = ~I915_READ(GEN8_EU_DISABLE1); in gen10_sseu_info_init()
318 eu_en = ~I915_READ(GEN8_EU_DISABLE2); in gen10_sseu_info_init()
[all …]
H A Di915_irq.c272 val = I915_READ(PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
349 old_val = I915_READ(GEN8_DE_PORT_IMR); in bdw_update_port_irq()
403 u32 sdeimr = I915_READ(SDEIMR); in ibx_display_interrupt_update()
656 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
931 misccpctl = I915_READ(GEN7_MISCCPCTL); in ivb_parity_work()
946 error_status = I915_READ(reg); in ivb_parity_work()
1250 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
1258 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1259 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1260 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
[all …]
H A Dintel_pm.c69 I915_READ(CHICKEN_PAR1_1) | in gen9_init_clock_gating()
75 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
79 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
83 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
88 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
93 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
103 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
110 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
117 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
138 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
[all …]

12