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Searched refs:CSR_WRITE_1 (Results 1 – 25 of 30) sorted by relevance

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/netbsd-src/sys/arch/evbarm/stand/boot2440/
H A Ddm9000.c148 CSR_WRITE_1(struct local *l, int reg, int data) in CSR_WRITE_1() function
200 CSR_WRITE_1(l, NCR, 0); /* use internal PHY */ in dm9k_init()
204 CSR_WRITE_1(l, GPR, GPR_PHYPWROFF); in dm9k_init()
206 CSR_WRITE_1(l, IMR, 0); in dm9k_init()
207 CSR_WRITE_1(l, TCR, 0); in dm9k_init()
208 CSR_WRITE_1(l, RCR, 0); in dm9k_init()
211 CSR_WRITE_1(l, NCR, NCR_RST); in dm9k_init()
217 CSR_WRITE_1(l, GPR, 0); in dm9k_init()
220 CSR_WRITE_1(l, NCR, NCR_RST); in dm9k_init()
230 CSR_WRITE_1(l, PAR + 0, en[0]); in dm9k_init()
[all …]
/netbsd-src/sys/arch/sandpoint/stand/altboot/
H A Ddsk.c60 #define CSR_WRITE_1(r,v) out8(r,v) macro
184 CSR_WRITE_1(chan->ctl, ATA_DREQ); in perform_atareset()
186 CSR_WRITE_1(chan->ctl, ATA_SRST|ATA_DREQ); in perform_atareset()
188 CSR_WRITE_1(chan->ctl, ATA_DREQ); in perform_atareset()
199 CSR_WRITE_1(chan->cmd + _NSECT, 0); in wakeup_drive()
200 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_IDLE); in wakeup_drive()
203 CSR_WRITE_1(chan->cmd + _NSECT, 0); in wakeup_drive()
204 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_STANDBY); in wakeup_drive()
214 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_CHKPWR); in atachkpwr()
227 CSR_WRITE_1(chan->cmd + _CMD, ATA_CMD_IDENT); in probe_drive()
[all …]
H A Dvge.c47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) macro
230 CSR_WRITE_1(l, VR_CTL1, val); in vge_init()
276 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR); in vge_init()
277 CSR_WRITE_1(l, VR_CAMADR, CAM_EN | SADR_CAM | 0); in vge_init()
279 CSR_WRITE_1(l, VR_CAM0 + i, en[i]); in vge_init()
280 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR | CAMCTL_WR); in vge_init()
285 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_VBIT); in vge_init()
286 CSR_WRITE_1(l, VR_CAM0, 01); in vge_init()
288 CSR_WRITE_1(l, VR_CAM0 + i, 00); in vge_init()
289 CSR_WRITE_1(l, VR_CAMADR, 0); in vge_init()
[all …]
H A Dnvt.c47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) macro
183 CSR_WRITE_1(l, VR_CTL1, val); in nvt_init()
230 CSR_WRITE_1(l, VR_RCR, 0); in nvt_init()
231 CSR_WRITE_1(l, VR_TCR, 0); in nvt_init()
235 CSR_WRITE_1(l, VR_CTL1, CTL1_FDX); in nvt_init()
236 CSR_WRITE_1(l, VR_CTL0, CTL0_START); in nvt_init()
237 CSR_WRITE_1(l, VR_CTL0, l->ctl0); in nvt_init()
259 CSR_WRITE_1(l, VR_CTL0, l->ctl0 | CTL0_TDMD); in nvt_send()
319 CSR_WRITE_1(l, VR_MIICR, 0); in mii_autopoll()
324 CSR_WRITE_1(l, VR_MIICR, MIICR_MAUTO); in mii_autopoll()
[all …]
H A Dfxp.c89 #define CSR_WRITE_1(l, r, v) out8((l)->iobase+(r), (v)) macro
221 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); in fxp_init()
224 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); in fxp_init()
277 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); in fxp_init()
300 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); in fxp_init()
321 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); in fxp_init()
352 CSR_WRITE_1(l, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); in fxp_send()
373 CSR_WRITE_1(l, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_RESUME); in fxp_recv()
401 CSR_WRITE_1(l, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_RESUME); in fxp_recv()
H A Drge.c47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) macro
159 CSR_WRITE_1(l, RGE_CR, CR_RESET); in rge_init()
171 CSR_WRITE_1(l, RGE_EECMD, EECMD_UNLOCK); in rge_init()
176 CSR_WRITE_1(l, RGE_EECMD, EECMD_LOCK); in rge_init()
218 CSR_WRITE_1(l, RGE_CR, CR_TXEN | CR_RXEN); in rge_init()
219 CSR_WRITE_1(l, RGE_ETTHR, 0x3f); in rge_init()
254 CSR_WRITE_1(l, RGE_TPPOLL, 0x40); in rge_send()
H A Dstg.c41 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) macro
207 CSR_WRITE_1(l, STGE_StationAddress0 + i, en[i]); in stg_init()
397 CSR_WRITE_1(l, STGE_PhyCtrl, v); in mii_read()
509 CSR_WRITE_1(l, STGE_PhyCtrl, v); in mii_bitbang_sync()
522 CSR_WRITE_1(l, STGE_PhyCtrl, v); in mii_bitbang_send()
529 CSR_WRITE_1(l, STGE_PhyCtrl, v); in mii_bitbang_send()
539 CSR_WRITE_1(l, STGE_PhyCtrl, v | PC_MgmtClk); in mii_bitbang_clk()
541 CSR_WRITE_1(l, STGE_PhyCtrl, v); in mii_bitbang_clk()
H A Dskg.c46 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) macro
251 CSR_WRITE_1(l, SK_RXMF1_CTRL_TEST, RFCTL_RESET_CLEAR); in skg_init()
253 CSR_WRITE_1(l, SK_TXMF1_CTRL_TEST, TFCTL_RESET_CLEAR); in skg_init()
289 CSR_WRITE_1(l, SK_TXAR1_COUNTERCTL, TXARCTL_ON|TXARCTL_FSYNC_ON); in skg_init()
/netbsd-src/sys/dev/ic/
H A Dcom.c139 #define CSR_WRITE_1(r, o, v) \ macro
483 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); in com_probe_subr()
484 CSR_WRITE_1(regs, COM_REG_IIR, 0); in com_probe_subr()
517 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); in com_enable_debugport()
519 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); in com_enable_debugport()
570 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); in com_attach_subr()
635 CSR_WRITE_1(regsp, COM_REG_FIFO, in com_attach_subr()
643 CSR_WRITE_1(regsp, COM_REG_FIFO, in com_attach_subr()
656 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); in com_attach_subr()
660 CSR_WRITE_1(regs in com_attach_subr()
[all...]
H A Drtl81x9.c146 CSR_WRITE_1(sc, RTK_EECMD, \
150 CSR_WRITE_1(sc, RTK_EECMD, \
194 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM); in rtk_read_eeprom()
217 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); in rtk_read_eeprom()
229 CSR_WRITE_1(sc, RTK_MII, \
233 CSR_WRITE_1(sc, RTK_MII, \
600 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); in rtk_reset()
1353 CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]); in rtk_init()
1369 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); in rtk_init()
1415 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); in rtk_init()
[all …]
H A Drtl8169.c425 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); in re_reset()
441 CSR_WRITE_1(sc, RTK_LDPS, 1); in re_reset()
779 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); in re_attach()
1506 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); in re_txeof()
1828 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); in re_start()
1830 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); in re_start()
1917 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); in re_init()
1924 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); in re_init()
1955 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); in re_init()
1967 CSR_WRITE_1(s in re_init()
[all...]
H A Dwivar.h236 #define CSR_WRITE_1(sc, reg, val) \ macro
258 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Drtl81x9var.h282 #define CSR_WRITE_1(sc, reg, val) \
281 #define CSR_WRITE_1( global() macro
H A Di82557var.h358 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Di82557.c247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); in fxp_scb_cmd()
1089 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); in fxp_intr()
1101 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); in fxp_intr()
2008 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); in fxp_init()
/netbsd-src/sys/dev/pci/
H A Dif_vge.c264 #define CSR_WRITE_1(sc, reg, val) \ macro
275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
380 CSR_WRITE_1(sc, VGE_EEADDR, addr); in vge_read_eeprom()
411 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_stop()
432 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_start()
433 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); in vge_miipoll_start()
449 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); in vge_miipoll_start()
480 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_readreg()
518 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_writereg()
[all …]
H A Dif_stge.c227 #define CSR_WRITE_1(_sc, reg, val) \ macro
1569 CSR_WRITE_1(sc, STGE_StationAddress0 + i, in stge_init()
1604 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); in stge_init()
1607 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64); in stge_init()
1613 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); in stge_init()
1614 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); in stge_init()
1620 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); in stge_init()
1621 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); in stge_init()
2041 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl); in stge_mii_bitbang_write()
H A Dif_ipwreg.h322 #define CSR_WRITE_1(sc, reg, val) \ macro
340 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
H A Dif_vr.c290 #define CSR_WRITE_1(sc, reg, val) \ macro
329 CSR_WRITE_1(sc, reg, \
333 CSR_WRITE_1(sc, reg, \
383 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); in vr_mii_bitbang_write()
394 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); in vr_mii_readreg()
406 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); in vr_mii_writereg()
477 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); in vr_setmulti()
517 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); in vr_setmulti()
H A Dif_iwireg.h546 #define CSR_WRITE_1(sc, reg, val) \ macro
564 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
H A Dif_msk.c277 CSR_WRITE_1(sc, reg, x); in sk_win_write_1()
945 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); in mskc_reset()
948 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); in mskc_reset()
949 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); in mskc_reset()
952 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); in mskc_reset()
954 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); in mskc_reset()
1024 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); in mskc_reset()
1025 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); in mskc_reset()
1031 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); in mskc_reset()
1032 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); in mskc_reset()
H A Dif_ale.c1398 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, in ale_rx_update_page()
1663 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); in ale_init()
1664 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); in ale_init()
/netbsd-src/sys/dev/sdmmc/
H A Dsbt.c40 #define CSR_WRITE_1(sc, reg, val) sdmmc_io_write_1((sc)->sc_sf, (reg), (val)) macro
188 CSR_WRITE_1(sc, SBT_REG_IENA, ISTAT_INTRD); in sbt_attach()
300 CSR_WRITE_1(sc, SBT_REG_RPC, 0); in sbt_read_packet()
304 CSR_WRITE_1(sc, SBT_REG_RPC, RPC_PCRRT); in sbt_read_packet()
310 CSR_WRITE_1(sc, SBT_REG_RPC, 0); in sbt_read_packet()
332 CSR_WRITE_1(sc, SBT_REG_ICLR, status); in sbt_intr()
/netbsd-src/sys/arch/evbarm/ixm1200/
H A Dnappi_nppb.c65 #define CSR_WRITE_1(sc, reg, val) \ macro
/netbsd-src/sys/arch/arm/xscale/
H A Dpxa2x0_mci.c147 #define CSR_WRITE_1(sc, reg, val) \ macro
986 CSR_WRITE_1(sc, MMC_TXFIFO, *cmd->c_buf++); in pxamci_intr_data()

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