Lines Matching refs:CSR_WRITE_1
47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) macro
230 CSR_WRITE_1(l, VR_CTL1, val); in vge_init()
276 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR); in vge_init()
277 CSR_WRITE_1(l, VR_CAMADR, CAM_EN | SADR_CAM | 0); in vge_init()
279 CSR_WRITE_1(l, VR_CAM0 + i, en[i]); in vge_init()
280 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR | CAMCTL_WR); in vge_init()
285 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_VBIT); in vge_init()
286 CSR_WRITE_1(l, VR_CAM0, 01); in vge_init()
288 CSR_WRITE_1(l, VR_CAM0 + i, 00); in vge_init()
289 CSR_WRITE_1(l, VR_CAMADR, 0); in vge_init()
290 CSR_WRITE_1(l, VR_CAMCTL, 0); in vge_init()
300 CSR_WRITE_1(l, VR_RDCSR, 01); in vge_init()
301 CSR_WRITE_1(l, VR_RDCSR, 04); in vge_init()
303 CSR_WRITE_1(l, VR_RCR, RCR_AP); in vge_init()
304 CSR_WRITE_1(l, VR_TCR, 0); in vge_init()
305 CSR_WRITE_1(l, VR_CTL0 + 0x4, CTL0_STOP); in vge_init()
306 CSR_WRITE_1(l, VR_CTL0, CTL0_TXON | CTL0_RXON | CTL0_START); in vge_init()
400 CSR_WRITE_1(l, VR_MIICR, 0); in mii_autopoll()
401 CSR_WRITE_1(l, VR_MIIADR, 1U << 7); in mii_autopoll()
406 CSR_WRITE_1(l, VR_MIICR, MIICR_MAUTO); in mii_autopoll()
418 CSR_WRITE_1(l, VR_MIICR, 0); in mii_stoppoll()
431 CSR_WRITE_1(l, VR_MIICFG, phy); in mii_read()
432 CSR_WRITE_1(l, VR_MIIADR, reg); in mii_read()
433 CSR_WRITE_1(l, VR_MIICR, MIICR_RCMD); in mii_read()
449 CSR_WRITE_1(l, VR_MIICFG, phy); in mii_write()
450 CSR_WRITE_1(l, VR_MIIADR, reg); in mii_write()
451 CSR_WRITE_1(l, VR_MIICR, MIICR_WCMD); in mii_write()