| /netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| H A D | exynos5410.h | 39 #define CLK_UART1 258 macro
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| H A D | actions,s500-cmu.h | 61 #define CLK_UART1 39 macro
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| H A D | actions,s700-cmu.h | 61 #define CLK_UART1 37 macro
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| H A D | actions,s900-cmu.h | 88 #define CLK_UART1 68 macro
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| H A D | pistachio-clk.h | 42 #define CLK_UART1 49 macro
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| H A D | exynos5250.h | 95 #define CLK_UART1 290 macro
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| H A D | s5pv210.h | 162 #define CLK_UART1 142 macro
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| H A D | exynos5420.h | 69 #define CLK_UART1 258 macro
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| H A D | exynos4.h | 153 #define CLK_UART1 313 macro
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| H A D | exynos3250.h | 223 #define CLK_UART1 215 macro
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| H A D | sprd,sc9860-clk.h | 88 #define CLK_UART1 3 macro
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| /netbsd-src/sys/arch/arm/nxp/ |
| H A D | imx8mq_ccm.c | 136 IMX_COMPOSITE(CLK_UART1, "uart1", uart_p, 0xaf00, 0),
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| H A D | imx8mq_ccm.h | 183 #define CLK_UART1 148 macro
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| /netbsd-src/sys/arch/mips/ingenic/ |
| H A D | apbus.c | 77 { "com", JZ_UART1, 50, CLK_UART1, 0, 0},
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| H A D | ingenic_regs.h | 170 #define CLK_UART1 (1 << 16) macro
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| H A D | s5pv210.dtsi | 335 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
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| H A D | owl-s500.dtsi | 144 clocks = <&cmu CLK_UART1>;
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| H A D | exynos5410.dtsi | 351 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| H A D | exynos3250.dtsi | 525 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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| H A D | exynos4.dtsi | 464 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| H A D | exynos5250.dtsi | 1212 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/ |
| H A D | whale2.dtsi | 91 <&ap_clk CLK_UART1>, <&ext_26m>;
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/actions/ |
| H A D | s700.dtsi | 127 clocks = <&cmu CLK_UART1>;
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| H A D | s900.dtsi | 133 clocks = <&cmu CLK_UART1>;
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/ |
| H A D | pistachio.dtsi | 272 clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
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