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Searched refs:CLK_TOP_MSDC50_0_SEL (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt7629-clk.h96 #define CLK_TOP_MSDC50_0_SEL 84 macro
H A Dmt7622-clk.h81 #define CLK_TOP_MSDC50_0_SEL 67 macro
H A Dmt6765-clk.h146 #define CLK_TOP_MSDC50_0_SEL 109 macro
H A Dmt8173-clk.h108 #define CLK_TOP_MSDC50_0_SEL 96 macro
H A Dmt2712-clk.h145 #define CLK_TOP_MSDC50_0_SEL 112 macro
H A Dmt8192-clk.h38 #define CLK_TOP_MSDC50_0_SEL 24 macro
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8173-elm.dtsi382 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
H A Dmt7622.dtsi687 <&topckgen CLK_TOP_MSDC50_0_SEL>;