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/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Di386-opc.tbl1069 $avx:AVX:66:Vex128|VexVVVV|VexW0|SSE2AVX:RegXMM:Xmmword, +
1074 $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, +
1090 movd, 0x666e, AVX, D|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXM…
1091 movd, 0x666e, AVX&x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM }
1097 movq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Reg…
1098 movq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|…
1099 movq, 0x666e, AVX&x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIn…
1157 $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, +
1173 cvtsi2ss, 0xf32a, AVX&x64, Modrm|Vex=3|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|A…
1174 cvtsi2ss, 0xf32a, AVX&x64, Modrm|Vex=3|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax,…
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H A DChangeLog-2008295 AVX Programming Reference (August, 2008)
317 * i386-opc.tbl: Add AES + AVX instructions.
377 * i386-reg.tbl: Use Dw2Inval on AVX registers.
558 instructions which don't have AVX equivalent.
783 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
785 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Di386.opt609 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
707 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
711 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code gener…
715 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and c…
719 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in fu…
723 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in fu…
727 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in fu…
731 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in fu…
735 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in fu…
739 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in fu…
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H A Dx86-tune.def519 /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
536 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
541 /* X86_TUNE_AVX256_OPTIMAL: Use 256-bit AVX instructions instead of 512-bit AVX
549 AVX instructions. */
554 AVX instructions. */
559 AVX instructions. */
564 AVX instructions. */
H A Di386-isa.def25 DEF_PTA(AVX)
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Di386.opt601 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
691 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
695 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code gener…
699 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and c…
703 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in fu…
707 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in fu…
711 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in fu…
715 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in fu…
719 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in fu…
723 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in fu…
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H A Dx86-tune.def450 /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
467 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
472 /* X86_TUNE_AVX256_OPTIMAL: Use 256-bit AVX instructions instead of 512-bit AVX
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86.td121 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
122 "Enable AVX instructions",
134 "Enable AVX-512 instructions",
137 "Enable AVX-512 Exponential and Reciprocal Instructions",
140 "Enable AVX-512 Conflict Detection Instructions",
143 "true", "Enable AVX-512 Population Count Instructions",
146 "Enable AVX-512 PreFetch Instructions",
152 "Enable AVX-512 Doubleword and Quadword Instructions",
155 "Enable AVX-512 Byte and Word Instructions",
158 "Enable AVX-512 Vector Length eXtensions",
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H A DX86InstrFormats.td501 // AVX instructions have a 'v' prefix in the mnemonic
518 // AVX instructions have a 'v' prefix in the mnemonic
532 // AVX instructions have a 'v' prefix in the mnemonic
547 // AVX instructions have a 'v' prefix in the mnemonic
570 // AVX instructions have a 'v' prefix in the mnemonic
581 // VSSI - SSE1 instructions with XS prefix in AVX form.
582 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
615 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
616 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
618 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
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H A DX86CallingConv.td223 // Boolean vectors of AVX-512 are returned in SIMD registers.
224 // The call from AVX to AVX-512 function should work,
225 // since the boolean types in AVX/AVX2 are promoted by default.
241 // supported while using the AVX target feature.
247 // supported while using the AVX-512 target feature.
544 // Boolean vectors of AVX-512 are passed in SIMD registers.
545 // The call from AVX to AVX-512 function should work,
546 // since the boolean types in AVX/AVX2 are promoted by default.
700 // AVX
704 // AVX-512
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H A DX86RegisterInfo.td251 // YMM0-15 registers, used by AVX instructions and
252 // YMM16-31 registers, used by AVX-512 instructions.
260 // ZMM Registers, used by AVX-512 instructions.
281 // Mask Registers, used by AVX-512 instructions.
589 // AVX-512 vector/mask registers.
597 // Scalar AVX-512 floating point registers.
602 // Extended VR128 and VR256 for AVX-512 instructions
H A DX86Subtarget.h62 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
634 bool hasAVX() const { return X86SSELevel >= AVX; } in hasAVX()
H A DX86ScheduleBtVer2.td25 // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
801 // AVX instructions.
829 // SSE2/AVX Store Selected Bytes of Double Quadword - (V)MASKMOVDQ
991 // AVX Zero-idioms.
1024 // AVX
1043 // AVX variants.
/netbsd-src/crypto/external/bsd/openssl.old/dist/doc/man3/
H A DOPENSSL_ia32cap.pod58 =item bit #60 denoting AVX extension;
121 ':~0x20' would disable AVX2 code paths, and ':0' - all post-AVX
132 AVX | 2.19 | 2.09 | 3.0
/netbsd-src/external/apache2/argon2/dist/phc-winner-argon2/
H A DCHANGELOG.md3 * AVX2/AVX-512F optimizations of BLAMKA
/netbsd-src/crypto/external/bsd/openssl/dist/doc/man3/
H A DOPENSSL_ia32cap.pod58 =item bit #60 denoting AVX extension;
123 C<:~0x20> would disable AVX2 code paths, and C<:0> - all post-AVX
/netbsd-src/external/apache2/llvm/dist/clang/lib/Basic/Targets/
H A DX86.cpp322 .Case("+avx", AVX) in handleTargetFeatures()
751 case AVX: in getTargetDefines()
782 case AVX: in getTargetDefines()
928 .Case("avx", SSELevel >= AVX) in hasFeature()
/netbsd-src/sys/external/isc/libsodium/dist/
H A Dconfigure.ac429 AC_MSG_CHECKING(for AVX instructions set)
432 # error NativeClient detected - Avoiding AVX opcodes
438 AC_DEFINE([HAVE_AVXINTRIN_H], [1], [AVX is available])
614 AC_MSG_CHECKING(whether we can assemble AVX opcodes)
628 AC_DEFINE([HAVE_AVX_ASM], [1], [AVX opcodes are supported])
/netbsd-src/sys/external/mit/xen-include-public/dist/xen/include/public/arch-x86/
H A Dcpufeatureset.h148 XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */
/netbsd-src/external/mit/isl/dist/m4/
H A Dax_cc_maxopt.m4126 *3?6[[ae]]?:*:*:*) icc_flags="-xCORE-AVX-I -xAVX -SSE4.2 -xS -xT -xB -xK" ;;
127 …*3?6[[cf]]?:*:*:*|*4?6[[56]]?:*:*:*) icc_flags="-xCORE-AVX2 -xCORE-AVX-I -xAVX -SSE4.2 -xS -xT -xB…
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/
H A Dconfig.in6 /* Define to 1 if the assembler supports AVX. */
/netbsd-src/external/gpl3/gcc/dist/libgcc/
H A Dconfig.in6 /* Define to 1 if the assembler supports AVX. */
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A DChangeLog-2008295 AVX Programming Reference (August, 2008)
317 * i386-opc.tbl: Add AES + AVX instructions.
377 * i386-reg.tbl: Use Dw2Inval on AVX registers.
558 instructions which don't have AVX equivalent.
783 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
785 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
/netbsd-src/external/gpl3/gdb/dist/opcodes/
H A DChangeLog-2008295 AVX Programming Reference (August, 2008)
317 * i386-opc.tbl: Add AES + AVX instructions.
377 * i386-reg.tbl: Use Dw2Inval on AVX registers.
558 instructions which don't have AVX equivalent.
783 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
785 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
/netbsd-src/external/gpl3/gdb.old/dist/opcodes/
H A DChangeLog-2008295 AVX Programming Reference (August, 2008)
317 * i386-opc.tbl: Add AES + AVX instructions.
377 * i386-reg.tbl: Use Dw2Inval on AVX registers.
558 instructions which don't have AVX equivalent.
783 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
785 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.

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