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Searched refs:ASR (Results 1 – 25 of 119) sorted by relevance

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/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Dc_dsp32alu_rrpmmp_sft.s20 R0 = R0 +|- R0 , R7 = R0 -|+ R0 (ASR);
21 R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR);
22 R2 = R0 +|- R2 , R5 = R0 -|+ R2 (ASR);
23 R3 = R0 +|- R3 , R4 = R0 -|+ R3 (ASR);
24 R4 = R0 +|- R4 , R3 = R0 -|+ R4 (ASR);
25 R5 = R0 +|- R5 , R2 = R0 -|+ R5 (ASR);
26 R6 = R0 +|- R6 , R1 = R0 -|+ R6 (ASR);
27 R7 = R0 +|- R7 , R0 = R0 -|+ R7 (ASR);
45 R0 = R1 +|- R0 , R7 = R1 -|+ R0 (ASR);
46 R1 = R1 +|- R1 , R6 = R1 -|+ R1 (ASR);
[all …]
H A Dc_dsp32alu_rrpmmp_sft_x.s19 R0 = R0 +|- R0 , R7 = R0 -|+ R0 (CO , ASR);
20 R1 = R0 +|- R1 , R6 = R0 -|+ R1 (CO , ASR);
21 R2 = R0 +|- R2 , R5 = R0 -|+ R2 (CO , ASR);
22 R3 = R0 +|- R3 , R4 = R0 -|+ R3 (CO , ASR);
23 R4 = R0 +|- R4 , R3 = R0 -|+ R4 (CO , ASR);
24 R5 = R0 +|- R5 , R2 = R0 -|+ R5 (CO , ASR);
25 R6 = R0 +|- R6 , R1 = R0 -|+ R6 (CO , ASR);
26 R7 = R0 +|- R7 , R0 = R0 -|+ R7 (CO , ASR);
44 R0 = R1 +|- R0 , R7 = R1 -|+ R0 (CO , ASR);
45 R1 = R1 +|- R1 , R6 = R1 -|+ R1 (CO , ASR);
[all …]
H A Dc_dsp32alu_rrppmm_sft.s19 R0 = R0 +|+ R0, R7 = R0 -|- R0 (ASR);
21 R2 = R0 +|+ R2, R5 = R0 -|- R2 (ASR);
22 R3 = R0 +|+ R3, R4 = R0 -|- R3 (ASR);
24 R5 = R0 +|+ R5, R2 = R0 -|- R5 (ASR);
26 R7 = R0 +|+ R7, R0 = R0 -|- R7 (ASR);
44 R0 = R1 +|+ R0, R7 = R1 -|- R0 (ASR);
45 R1 = R1 +|+ R1, R6 = R1 -|- R1 (ASR);
47 R3 = R1 +|+ R3, R4 = R1 -|- R3 (ASR);
48 R4 = R1 +|+ R4, R3 = R1 -|- R4 (ASR);
49 R5 = R1 +|+ R5, R2 = R1 -|- R5 (ASR);
[all …]
H A Dc_dsp32alu_rrppmm_sft_x.s19 R0 = R0 +|+ R0, R7 = R0 -|- R0 (CO , ASR);
21 R2 = R0 +|+ R2, R5 = R0 -|- R2 (CO , ASR);
22 R3 = R0 +|+ R3, R4 = R0 -|- R3 (CO , ASR);
24 R5 = R0 +|+ R5, R2 = R0 -|- R5 (CO , ASR);
26 R7 = R0 +|+ R7, R0 = R0 -|- R7 (CO , ASR);
44 R0 = R1 +|+ R0, R7 = R1 -|- R0 (CO , ASR);
45 R1 = R1 +|+ R1, R6 = R1 -|- R1 (CO , ASR);
47 R3 = R1 +|+ R3, R4 = R1 -|- R3 (CO , ASR);
48 R4 = R1 +|+ R4, R3 = R1 -|- R4 (CO , ASR);
49 R5 = R1 +|+ R5, R2 = R1 -|- R5 (CO , ASR);
[all …]
H A Dc_dsp32shift_bitmux.s19 BITMUX( R0 , R1, A0) (ASR);
20 BITMUX( R0 , R2, A0) (ASR);
21 BITMUX( R0 , R3, A0) (ASR);
22 BITMUX( R0 , R4, A0) (ASR);
23 BITMUX( R0 , R5, A0) (ASR);
24 BITMUX( R0 , R6, A0) (ASR);
25 BITMUX( R0 , R7, A0) (ASR);
48 BITMUX( R1 , R0, A0) (ASR);
50 BITMUX( R1 , R2, A0) (ASR);
51 BITMUX( R1 , R3, A0) (ASR);
[all …]
H A Dc_dsp32shift_vmaxvmax.s69 R1 = VIT_MAX( R1 , R0 ) (ASR);
70 R2 = VIT_MAX( R2 , R1 ) (ASR);
71 R3 = VIT_MAX( R3 , R2 ) (ASR);
72 R4 = VIT_MAX( R4 , R3 ) (ASR);
73 R5 = VIT_MAX( R5 , R4 ) (ASR);
74 R6 = VIT_MAX( R6 , R5 ) (ASR);
75 R7 = VIT_MAX( R7 , R6 ) (ASR);
76 R0 = VIT_MAX( R0 , R7 ) (ASR);
94 R0 = VIT_MAX( R4 , R0 ) (ASR);
95 R1 = VIT_MAX( R5 , R1 ) (ASR);
[all …]
H A Dc_dsp32shift_vmax.s70 R0.L = VIT_MAX( R0 ) (ASR);
71 R1.L = VIT_MAX( R1 ) (ASR);
72 R2.L = VIT_MAX( R2 ) (ASR);
73 R3.L = VIT_MAX( R3 ) (ASR);
74 R4.L = VIT_MAX( R4 ) (ASR);
75 R5.L = VIT_MAX( R5 ) (ASR);
76 R6.L = VIT_MAX( R6 ) (ASR);
77 R7.L = VIT_MAX( R7 ) (ASR);
95 R2.L = VIT_MAX( R0 ) (ASR);
96 R3.L = VIT_MAX( R1 ) (ASR);
[all …]
H A Dx1.s10 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
16 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
20 R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR);
32 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
37 R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR);
41 R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR);
H A Da30.s12 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
24 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
32 R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR);
46 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
H A Ds7.s17 R6 = VIT_MAX( R1 , R0 ) (ASR);
35 R6 = VIT_MAX( R1 , R0 ) (ASR);
55 R6 = VIT_MAX( R1 , R0 ) (ASR);
73 R6 = VIT_MAX( R1 , R0 ) (ASR);
H A Drandom_0012.S13 R4.L = VIT_MAX (R5) (ASR);
24 R3.L = VIT_MAX (R4) (ASR);
35 R2.L = VIT_MAX (R5) (ASR);
46 R6.L = VIT_MAX (R0) (ASR);
H A Dissue139.S20 R7 = R1 +|+ R0, R6 = R1 -|- R0 (SCO , ASR);
42 R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASR);
61 R5 = R1 +|+ R0, R4 = R1 -|- R0 (CO , ASR);
H A Ddsp_s1.s35 BITMUX( R0 , R1, A0) (ASR);
54 BITMUX( R0 , R4, A0) (ASR);
H A Dvit_max.s23 R7 = VIT_MAX (R1, R0) (ASR);
46 R3.L = VIT_MAX (R1) (ASR);
H A Dc_cc_regmvlogi_mvbrsft_sn.S45 R0 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
50 R1 = R0 +|- R1 , R5 = R0 -|+ R1 (ASR); // dsp32alu sft
H A Dsri.s12 BITMUX( R6 , R7, A0) (ASR);
H A Dviterbi2.s132 R6 = VIT_MAX( R5 , R4 ) (ASR) || R3.L = W [ I1 ++ ] || NOP;
144 R6 = VIT_MAX( R5 , R4 ) (ASR);
H A Ds8.s46 R6.L = VIT_MAX( R1 ) (ASR);
H A Dc_cc_regmvlogi_mvbrsft_s1.s32 R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
H A Dc_cc_flagdreg_mvbrsft_s1.s86 R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
/netbsd-src/sys/arch/m68k/fpsp/
H A Dslogn.sa378 ASR.L #8,D0
379 ASR.L #8,D0 ...SHIFTED 16 BITS, BIASED EXPO. OF X
392 ASR.L #8,D0
393 ASR.L #8,D0
394 ASR.L #4,D0 ...SHIFTED 20, D0 IS THE DISPLACEMENT
573 ASR.L #8,D0
574 ASR.L #8,D0
575 ASR.L #4,D0 ...D0 CONTAINS DISPLACEMENT FOR 1/F
591 ASR.L #8,D0
592 ASR.L #8,D0
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
89 defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h36 ASR, enumerator
57 case AArch64_AM::ASR: return "asr"; in getShiftExtendName()
78 case 2: return AArch64_AM::ASR; in getShiftType()
106 case AArch64_AM::ASR: STEnc = 2; break; in getShifterImm()
/netbsd-src/external/gpl3/binutils/dist/gas/config/
H A Dbfin-parse.h175 ASR = 376, /* ASR */ enumerator
354 #define ASR 376 macro
/netbsd-src/external/gpl3/binutils.old/dist/gas/config/
H A Dbfin-parse.h175 ASR = 376, /* ASR */ enumerator
354 #define ASR 376 macro

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