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Searched refs:src_scc (Results 1 – 25 of 102) sorted by relevance

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/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_vop3_from_vopcx.s26 v_cmpx_class_f16_e64 m0, src_scc
27 // GFX11: v_cmpx_class_f16_e64 m0, src_scc ; encoding: [0x7e,0x00,0xfd,0xd4,0x7d,0xfa,0x01,0x00]
44 v_cmpx_class_f16_e64 src_scc, vcc_lo
45 // GFX11: v_cmpx_class_f16_e64 src_scc, vcc_lo ; encoding: [0x7e,0x00,0xfd,0xd4,0xfd,0xd4,0x00,0x00]
80 v_cmpx_class_f32_e64 ttmp15, src_scc
81 // GFX11: v_cmpx_class_f32_e64 ttmp15, src_scc ; encoding: [0x7e,0x00,0xfe,0xd4,0x7b,0xfa,0x01,0x00]
101 v_cmpx_class_f32_e64 src_scc, vcc_lo
102 // GFX11: v_cmpx_class_f32_e64 src_scc, vcc_lo ; encoding: [0x7e,0x00,0xfe,0xd4,0xfd,0xd4,0x00,0x00]
146 v_cmpx_class_f64_e64 -|src_scc|, src_scc
[all...]
H A Dgfx12_asm_vop3cx.s26 v_cmpx_class_f16_e64 m0, src_scc
27 // GFX12: v_cmpx_class_f16_e64 m0, src_scc ; encoding: [0x7e,0x00,0xfd,0xd4,0x7d,0xfa,0x01,0x00]
44 v_cmpx_class_f16_e64 src_scc, vcc_lo
45 // GFX12: v_cmpx_class_f16_e64 src_scc, vcc_lo ; encoding: [0x7e,0x00,0xfd,0xd4,0xfd,0xd4,0x00,0x00]
77 v_cmpx_class_f32_e64 ttmp15, src_scc
78 // GFX12: v_cmpx_class_f32_e64 ttmp15, src_scc ; encoding: [0x7e,0x00,0xfe,0xd4,0x7b,0xfa,0x01,0x00]
98 v_cmpx_class_f32_e64 src_scc, vcc_lo
99 // GFX12: v_cmpx_class_f32_e64 src_scc, vcc_lo ; encoding: [0x7e,0x00,0xfe,0xd4,0xfd,0xd4,0x00,0x00]
143 v_cmpx_class_f64_e64 -|src_scc|, src_scc
[all...]
H A Dgfx11_asm_vop3_from_vopc.s35 v_cmp_class_f16_e64 s5, m0, src_scc
36 // W32: v_cmp_class_f16_e64 s5, m0, src_scc ; encoding: [0x05,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
59 v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo
60 // W32: v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo ; encoding: [0x7b,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
95 v_cmp_class_f16_e64 s[10:11], m0, src_scc
96 // W64: v_cmp_class_f16_e64 s[10:11], m0, src_scc ; encoding: [0x0a,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
119 v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo
120 // W64: v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
170 v_cmp_class_f32_e64 s5, ttmp15, src_scc
171 // W32: v_cmp_class_f32_e64 s5, ttmp15, src_scc ; encodin
[all...]
H A Dgfx11_asm_vop3.s25 v_add3_u32 v5, ttmp15, src_scc, ttmp15
26 // GFX11: v_add3_u32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x55,0xd6,0x7b,0xfa,0xed,0x01]
40 v_add3_u32 v5, -1, exec_hi, src_scc
41 // GFX11: v_add3_u32 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x00,0x55,0xd6,0xc1,0xfe,0xf4,0x03]
46 v_add3_u32 v5, src_scc, vcc_lo, -1
47 // GFX11: v_add3_u32 v5, src_scc, vcc_lo, -1 ; encoding: [0x05,0x00,0x55,0xd6,0xfd,0xd4,0x04,0x03]
76 v_add_co_u32 v5, s6, ttmp15, src_scc
77 // W32: v_add_co_u32 v5, s6, ttmp15, src_scc ; encoding: [0x05,0x06,0x00,0xd7,0x7b,0xfa,0x01,0x00]
104 v_add_co_u32 v5, ttmp15, src_scc, vcc_lo
105 // W32: v_add_co_u32 v5, ttmp15, src_scc, vcc_l
[all...]
H A Dgfx12_asm_vop3c.s35 v_cmp_class_f16_e64 s5, m0, src_scc
36 // W32: v_cmp_class_f16_e64 s5, m0, src_scc ; encoding: [0x05,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
59 v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo
60 // W32: v_cmp_class_f16_e64 ttmp15, src_scc, vcc_lo ; encoding: [0x7b,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
91 v_cmp_class_f16_e64 s[10:11], m0, src_scc
92 // W64: v_cmp_class_f16_e64 s[10:11], m0, src_scc ; encoding: [0x0a,0x00,0x7d,0xd4,0x7d,0xfa,0x01,0x00]
115 v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo
116 // W64: v_cmp_class_f16_e64 ttmp[14:15], src_scc, vcc_lo ; encoding: [0x7a,0x00,0x7d,0xd4,0xfd,0xd4,0x00,0x00]
166 v_cmp_class_f32_e64 s5, ttmp15, src_scc
167 // W32: v_cmp_class_f32_e64 s5, ttmp15, src_scc ; encodin
[all...]
H A Dgfx12_asm_vop3.s25 v_add3_u32 v5, ttmp15, src_scc, ttmp15
26 // GFX12: v_add3_u32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x55,0xd6,0x7b,0xfa,0xed,0x01]
40 v_add3_u32 v5, -1, exec_hi, src_scc
41 // GFX12: v_add3_u32 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x00,0x55,0xd6,0xc1,0xfe,0xf4,0x03]
46 v_add3_u32 v5, src_scc, vcc_lo, -1
47 // GFX12: v_add3_u32 v5, src_scc, vcc_lo, -1 ; encoding: [0x05,0x00,0x55,0xd6,0xfd,0xd4,0x04,0x03]
76 v_add_co_u32 v5, s6, ttmp15, src_scc
77 // W32: v_add_co_u32 v5, s6, ttmp15, src_scc ; encoding: [0x05,0x06,0x00,0xd7,0x7b,0xfa,0x01,0x00]
104 v_add_co_u32 v5, ttmp15, src_scc, vcc_lo
105 // W32: v_add_co_u32 v5, ttmp15, src_scc, vcc_l
[all...]
H A Dgfx10_unsupported.s794 s_and_not1_b32 exec_hi, src_scc, vcc_lo
797 s_and_not1_b64 exec, src_scc, exec
836 s_cls_i32 exec_hi, src_scc
839 s_cls_i32_i64 exec_hi, src_scc
842 s_clz_i32_u32 exec_hi, src_scc
845 s_clz_i32_u64 exec_hi, src_scc
848 s_ctz_i32_b32 exec_hi, src_scc
851 s_ctz_i32_b64 exec_hi, src_scc
884 s_or_not1_b32 exec_hi, src_scc, vcc_lo
887 s_or_not1_b64 exec, src_scc, exe
[all...]
H A Dgfx11_asm_vop3_from_vop2.s11 v_add_co_ci_u32_e64 v5, s6, v255, src_scc, s3
12 // W32: v_add_co_ci_u32_e64 v5, s6, v255, src_scc, s3 ; encoding: [0x05,0x06,0x20,0xd5,0xff,0xfb,0x0d,0x00]
55 v_add_co_ci_u32_e64 v5, ttmp15, src_scc, null, ttmp15
56 // W32: v_add_co_ci_u32_e64 v5, ttmp15, src_scc, null, ttmp15 ; encoding: [0x05,0x7b,0x20,0xd5,0xfd,0xf8,0xec,0x01]
63 v_add_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7]
64 // W64: v_add_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0xff,0xfb,0x19,0x00]
107 v_add_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15]
108 // W64: v_add_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15] ; encoding: [0x05,0x7a,0x20,0xd5,0xfd,0xf8,0xe8,0x01]
132 v_add_f16_e64 v5.l, ttmp15, src_scc
133 // GFX11: v_add_f16_e64 v5.l, ttmp15, src_scc ; encodin
[all...]
H A Dgfx11_asm_vop3p.s24 v_dot2_f32_bf16 v5, ttmp15, src_scc, ttmp15
42 v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc neg_lo:[1,0,0] neg_hi:[1,0,0]
66 v_dot2_f32_f16 v5, ttmp15, src_scc, ttmp15
81 v_dot2_f32_f16 v5, -1, exec_hi, src_scc
87 v_dot2_f32_f16 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0] neg_hi:[0,1,0]
111 v_dot4_i32_iu8 v5, ttmp15, src_scc, ttmp15
126 v_dot4_i32_iu8 v5, -1, exec_hi, src_scc
132 v_dot4_i32_iu8 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0]
156 v_dot4_u32_u8 v5, ttmp15, src_scc, ttmp15
171 v_dot4_u32_u8 v5, -1, exec_hi, src_scc
[all …]
H A Dgfx12_asm_vop3_from_vop2.s11 v_add_co_ci_u32_e64 v5, s6, v255, src_scc, s3
12 // W32: v_add_co_ci_u32_e64 v5, s6, v255, src_scc, s3 ; encoding: [0x05,0x06,0x20,0xd5,0xff,0xfb,0x0d,0x00]
55 v_add_co_ci_u32_e64 v5, ttmp15, src_scc, null, ttmp15
56 // W32: v_add_co_ci_u32_e64 v5, ttmp15, src_scc, null, ttmp15 ; encoding: [0x05,0x7b,0x20,0xd5,0xfd,0xf8,0xec,0x01]
63 v_add_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7]
64 // W64: v_add_co_ci_u32_e64 v5, s[12:13], v255, src_scc, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0xff,0xfb,0x19,0x00]
107 v_add_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15]
108 // W64: v_add_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15] ; encoding: [0x05,0x7a,0x20,0xd5,0xfd,0xf8,0xe8,0x01]
132 v_add_f16_e64 v5.l, ttmp15, src_scc
133 // GFX12: v_add_f16_e64 v5.l, ttmp15, src_scc ; encodin
[all...]
H A Dgfx12_asm_vop3p.s24 v_dot2_f32_bf16 v5, ttmp15, src_scc, ttmp15
42 v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc neg_lo:[1,0,0] neg_hi:[1,0,0]
66 v_dot2_f32_f16 v5, ttmp15, src_scc, ttmp15
81 v_dot2_f32_f16 v5, -1, exec_hi, src_scc
87 v_dot2_f32_f16 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0] neg_hi:[0,1,0]
111 v_dot4_i32_iu8 v5, ttmp15, src_scc, ttmp15
126 v_dot4_i32_iu8 v5, -1, exec_hi, src_scc
132 v_dot4_i32_iu8 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0]
156 v_dot4_u32_u8 v5, ttmp15, src_scc, ttmp15
171 v_dot4_u32_u8 v5, -1, exec_hi, src_scc
[all …]
H A Dgfx11_asm_vopcx.s44 v_cmpx_class_f16 src_scc, v2.l
45 // GFX11: v_cmpx_class_f16_e32 src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7d]
59 v_cmpx_class_f16 src_scc, v2.h
60 // GFX11: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
104 v_cmpx_class_f32 src_scc, v2
105 // GFX11: v_cmpx_class_f32_e32 src_scc, v2 ; encoding: [0xfd,0x04,0xfc,0x7d]
140 v_cmpx_class_f64 src_scc, v2
141 // GFX11: v_cmpx_class_f64_e32 src_scc, v2 ; encoding: [0xfd,0x04,0xfe,0x7d]
185 v_cmpx_eq_f16 src_scc, v2.l
186 // GFX11: v_cmpx_eq_f16_e32 src_scc, v
[all...]
H A Dgfx12_asm_vopcx.s44 v_cmpx_class_f16 src_scc, v2.l
45 // GFX12: v_cmpx_class_f16_e32 src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7d]
56 v_cmpx_class_f16 src_scc, v2.h
57 // GFX12: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
101 v_cmpx_class_f32 src_scc, v2
102 // GFX12: v_cmpx_class_f32_e32 src_scc, v2 ; encoding: [0xfd,0x04,0xfc,0x7d]
137 v_cmpx_class_f64 src_scc, v2
138 // GFX12: v_cmpx_class_f64_e32 src_scc, v2 ; encoding: [0xfd,0x04,0xfe,0x7d]
182 v_cmpx_eq_f16 src_scc, v2.l
183 // GFX12: v_cmpx_eq_f16_e32 src_scc, v
[all...]
H A Dgfx12_asm_vop1.s46 v_bfrev_b32 v5, src_scc
47 // GFX12: v_bfrev_b32_e32 v5, src_scc ; encoding: [0xfd,0x70,0x0a,0x7e]
91 v_ceil_f16 v5.l, src_scc
92 // GFX12: v_ceil_f16_e32 v5.l, src_scc ; encoding: [0xfd,0xb8,0x0a,0x7e]
136 v_ceil_f32 v5, src_scc
137 // GFX12: v_ceil_f32_e32 v5, src_scc ; encoding: [0xfd,0x44,0x0a,0x7e]
172 v_ceil_f64 v[5:6], src_scc
173 // GFX12: v_ceil_f64_e32 v[5:6], src_scc ; encoding: [0xfd,0x30,0x0a,0x7e]
217 v_cls_i32 v5, src_scc
218 // GFX12: v_cls_i32_e32 v5, src_scc ; encodin
[all...]
H A Dgfx11_asm_vop1.s44 v_bfrev_b32 v5, src_scc
45 // GFX11: v_bfrev_b32_e32 v5, src_scc ; encoding: [0xfd,0x70,0x0a,0x7e]
95 v_ceil_f16 v5.h, src_scc
96 // GFX11: v_ceil_f16_e32 v5.h, src_scc ; encoding: [0xfd,0xb8,0x0a,0x7f]
140 v_ceil_f32 v5, src_scc
141 // GFX11: v_ceil_f32_e32 v5, src_scc ; encoding: [0xfd,0x44,0x0a,0x7e]
176 v_ceil_f64 v[5:6], src_scc
177 // GFX11: v_ceil_f64_e32 v[5:6], src_scc ; encoding: [0xfd,0x30,0x0a,0x7e]
221 v_cls_i32 v5, src_scc
222 // GFX11: v_cls_i32_e32 v5, src_scc ; encodin
[all...]
H A Dgfx11_asm_vop3_from_vop1.s43 v_bfrev_b32_e64 v5, src_scc
44 // GFX11: v_bfrev_b32_e64 v5, src_scc ; encoding: [0x05,0x00,0xb8,0xd5,0xfd,0x00,0x00,0x00]
88 v_ceil_f16_e64 v5, src_scc mul:4
89 // GFX11: v_ceil_f16_e64 v5, src_scc mul:4 ; encoding: [0x05,0x00,0xdc,0xd5,0xfd,0x00,0x00,0x10]
133 v_ceil_f32_e64 v5, src_scc mul:4
134 // GFX11: v_ceil_f32_e64 v5, src_scc mul:4 ; encoding: [0x05,0x00,0xa2,0xd5,0xfd,0x00,0x00,0x10]
169 v_ceil_f64_e64 v[5:6], -|src_scc| mul:4
170 // GFX11: v_ceil_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0x98,0xd5,0xfd,0x00,0x00,0x30]
214 v_cls_i32_e64 v5, src_scc
215 // GFX11: v_cls_i32_e64 v5, src_scc ; encodin
[all...]
H A Dgfx12_asm_vop3_from_vop1.s43 v_bfrev_b32_e64 v5, src_scc
44 // GFX12: v_bfrev_b32_e64 v5, src_scc ; encoding: [0x05,0x00,0xb8,0xd5,0xfd,0x00,0x00,0x00]
88 v_ceil_f16_e64 v5, src_scc mul:4
89 // GFX12: v_ceil_f16_e64 v5, src_scc mul:4 ; encoding: [0x05,0x00,0xdc,0xd5,0xfd,0x00,0x00,0x10]
133 v_ceil_f32_e64 v5, src_scc mul:4
134 // GFX12: v_ceil_f32_e64 v5, src_scc mul:4 ; encoding: [0x05,0x00,0xa2,0xd5,0xfd,0x00,0x00,0x10]
169 v_ceil_f64_e64 v[5:6], -|src_scc| mul:4
170 // GFX12: v_ceil_f64_e64 v[5:6], -|src_scc| mul:4 ; encoding: [0x05,0x01,0x98,0xd5,0xfd,0x00,0x00,0x30]
214 v_cls_i32_e64 v5, src_scc
215 // GFX12: v_cls_i32_e64 v5, src_scc ; encodin
[all...]
H A Dgfx12_asm_vopc.s59 v_cmp_class_f16 vcc_lo, src_scc, v2.l
60 // W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c]
119 v_cmp_class_f16 vcc, src_scc, v2.l
120 // W64: v_cmp_class_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c]
143 v_cmp_class_f16 vcc_lo, src_scc, v2.h
144 // W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c]
147 v_cmp_class_f16 vcc, src_scc, v2.h
148 // W64: v_cmp_class_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c]
211 v_cmp_class_f32 vcc_lo, src_scc, v2
212 // W32: v_cmp_class_f32_e32 vcc_lo, src_scc, v
[all...]
H A Dgfx9_asm_sopc.s51 s_cmp_eq_i32 src_scc, s2
105 s_cmp_eq_i32 s1, src_scc
162 s_cmp_lg_i32 src_scc, s2
216 s_cmp_lg_i32 s1, src_scc
273 s_cmp_gt_i32 src_scc, s2
327 s_cmp_gt_i32 s1, src_scc
384 s_cmp_ge_i32 src_scc, s2
438 s_cmp_ge_i32 s1, src_scc
495 s_cmp_lt_i32 src_scc, s2
549 s_cmp_lt_i32 s1, src_scc
[all …]
H A Dgfx11_asm_vopc.s59 v_cmp_class_f16 vcc_lo, src_scc, v2.l
60 // W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c]
119 v_cmp_class_f16 vcc, src_scc, v2.l
120 // W64: v_cmp_class_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7c]
151 v_cmp_class_f16 vcc_lo, src_scc, v2.h
152 // W32: v_cmp_class_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c]
155 v_cmp_class_f16 vcc, src_scc, v2.h
156 // W64: v_cmp_class_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7c]
219 v_cmp_class_f32 vcc_lo, src_scc, v2
220 // W32: v_cmp_class_f32_e32 vcc_lo, src_scc, v
[all...]
H A Dgfx8_asm_sopc.s63 s_cmp_eq_i32 src_scc, s2
129 s_cmp_eq_i32 s1, src_scc
198 s_cmp_lg_i32 src_scc, s2
264 s_cmp_lg_i32 s1, src_scc
333 s_cmp_gt_i32 src_scc, s2
399 s_cmp_gt_i32 s1, src_scc
468 s_cmp_ge_i32 src_scc, s2
534 s_cmp_ge_i32 s1, src_scc
603 s_cmp_lt_i32 src_scc, s2
669 s_cmp_lt_i32 s1, src_scc
[all …]
H A Dgfx12_asm_vop2.s59 v_add_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo
60 // W32: v_add_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x40]
119 v_add_co_ci_u32 v5, vcc, src_scc, v2, vcc
120 // W64: v_add_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x40]
166 v_add_f16 v5.l, src_scc, v2.l
167 // GFX12: v_add_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x64]
178 v_add_f16 v5.h, src_scc, v2.h
179 // GFX12: v_add_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x65]
223 v_add_f32 v5, src_scc, v2
224 // GFX12: v_add_f32_e32 v5, src_scc, v
[all...]
H A Dgfx11_asm_vop2.s59 v_add_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo
60 // W32: v_add_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x40]
119 v_add_co_ci_u32 v5, vcc, src_scc, v2, vcc
120 // W64: v_add_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x40]
166 v_add_f16 v5.l, src_scc, v2.l
167 // GFX11: v_add_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x64]
181 v_add_f16 v5.h, src_scc, v2.h
182 // GFX11: v_add_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x65]
226 v_add_f32 v5, src_scc, v2
227 // GFX11: v_add_f32_e32 v5, src_scc, v
[all...]
H A Dgfx12_asm_vopd.s61 v_dual_add_f32 v255, src_scc, v2 :: v_dual_add_f32 v6, -1, v3
69 v_dual_add_f32 v255, -1, v4 :: v_dual_add_f32 v6, src_scc, v5
133 v_dual_add_f32 v255, src_scc, v2 :: v_dual_add_nc_u32 v6, -1, v3
141 v_dual_add_f32 v255, -1, v4 :: v_dual_add_nc_u32 v6, src_scc, v5
205 v_dual_add_f32 v255, src_scc, v2 :: v_dual_and_b32 v6, -1, v3
213 v_dual_add_f32 v255, -1, v4 :: v_dual_and_b32 v6, src_scc, v5
277 v_dual_add_f32 v255, src_scc, v2 :: v_dual_cndmask_b32 v6, -1, v3
285 v_dual_add_f32 v255, -1, v4 :: v_dual_cndmask_b32 v6, src_scc, v5
349 v_dual_add_f32 v255, src_scc, v2 :: v_dual_dot2acc_f32_f16 v6, -1, v3
357 v_dual_add_f32 v255, -1, v4 :: v_dual_dot2acc_f32_f16 v6, src_scc, v
[all...]
H A Dgfx7_asm_sopc.s63 s_cmp_eq_i32 src_scc, s2
129 s_cmp_eq_i32 s1, src_scc
198 s_cmp_lg_i32 src_scc, s2
264 s_cmp_lg_i32 s1, src_scc
333 s_cmp_gt_i32 src_scc, s2
399 s_cmp_gt_i32 s1, src_scc
468 s_cmp_ge_i32 src_scc, s2
534 s_cmp_ge_i32 s1, src_scc
603 s_cmp_lt_i32 src_scc, s2
669 s_cmp_lt_i32 s1, src_scc
[all …]

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