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/llvm-project/llvm/test/CodeGen/NVPTX/
H A Dbf16-instructions.ll20 ; SM70-NEXT: .reg .b16 %rs<2>;
45 ; SM80-NEXT: .reg .b16 %rs<5>;
57 ; SM80-FTZ-NEXT: .reg .b16 %rs<4>;
72 ; SM90-NEXT: .reg .b16 %rs<4>;
88 ; SM70-NEXT: .reg .b16 %rs<2>;
113 ; SM80-NEXT: .reg .b16 %rs<5>;
125 ; SM80-FTZ-NEXT: .reg .b16 %rs<4>;
140 ; SM90-NEXT: .reg .b16 %rs<4>;
156 ; SM70-NEXT: .reg .b16 %rs<5>;
211 ; SM80-FTZ-NEXT: .reg .b16 %rs<
[all...]
H A Dvector-loads.ll104 ; CHECK: mov.b32 {%rs
105 ; CHECK: mov.b32 {%rs
106 ; CHECK: mov.b32 {%rs
107 ; CHECK: mov.b32 {%rs
108 ; CHECK: cvt.f32.f16 %f{{.*}}, %rs
109 ; CHECK: cvt.f32.f16 %f{{.*}}, %rs
110 ; CHECK: cvt.f32.f16 %f{{.*}}, %rs
111 ; CHECK: cvt.f32.f16 %f{{.*}}, %rs
112 ; CHECK: cvt.f32.f16 %f{{.*}}, %rs
113 ; CHECK: cvt.f32.f16 %f{{.*}}, %rs
[all...]
H A Df16x2-instructions.ll49 ; CHECK-NEXT: .reg .b16 %rs<2>;
64 ; CHECK-NEXT: .reg .b16 %rs<2>;
80 ; CHECK-NEXT: .reg .b16 %rs<4>;
110 ; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
149 ; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
183 ; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
217 ; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
255 ; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
290 ; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
317 ; CHECK-NEXT: .reg .b16 %rs<
[all...]
H A Dpr13291-i1-store.ll7 ; PTX32: mov.b16 %rs{{[0-9]+}}, 0;
8 ; PTX32-NEXT: st.global.u8 [%r{{[0-9]+}}], %rs{{[0-9]+}};
9 ; PTX64: mov.b16 %rs{{[0-9]+}}, 0;
10 ; PTX64-NEXT: st.global.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}};
17 ; PTX32: ld.global.u8 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
18 ; PTX32: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
19 ; PTX32: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
20 ; PTX64: ld.global.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
21 ; PTX64: and.b16 %rs{{[
[all...]
H A Df16-instructions.ll46 ; CHECK: mov.b16 [[R:%rs[0-9]+]], 0x3C00;
54 ; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fadd_param_0];
55 ; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fadd_param_1];
56 ; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]];
57 ; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%rs[0-9]+]], [[A]], [[B]];
61 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[R32]]
70 ; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_fadd_v1f16_param_0];
71 ; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_fadd_v1f16_param_1];
72 ; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%rs[0-9]+]], [[A]], [[B]];
73 ; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%rs[
[all...]
H A Darithmetic-int.ll228 ; CHECK: add.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
235 ; CHECK: sub.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
242 ; CHECK: mul.lo.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
249 ; CHECK: div.s16 %rs{{[
[all...]
H A Di16x2-instructions.ll38 ; COMMON-NEXT: .reg .b16 %rs<2>;
54 ; COMMON-NEXT: .reg .b16 %rs<2>;
71 ; COMMON-NEXT: .reg .b16 %rs<4>;
102 ; NO-I16x2-NEXT: .reg .b16 %rs<7>;
134 ; NO-I16x2-NEXT: .reg .b16 %rs<5>;
163 ; NO-I16x2-NEXT: .reg .b16 %rs<5>;
181 ; COMMON-NEXT: .reg .b16 %rs<7>;
212 ; NO-I16x2-NEXT: .reg .b16 %rs<7>;
244 ; NO-I16x2-NEXT: .reg .b16 %rs<7>;
276 ; NO-I16x2-NEXT: .reg .b16 %rs<
[all...]
H A Dbf16x2-instructions.ll52 ; SM80-NEXT: .reg .b16 %rs<4>;
63 ; SM90-NEXT: .reg .b16 %rs<4>;
132 ; CHECK-NEXT: .reg .b16 %rs<5>;
188 ; CHECK-NEXT: .reg .b16 %rs<2>;
240 ; CHECK-NEXT: .reg .b16 %rs<3>;
260 ; SM80-NEXT: .reg .b16 %rs<11>;
288 ; SM90-NEXT: .reg .b16 %rs<7>;
313 ; SM80-NEXT: .reg .b16 %rs<5>;
361 ; CHECK-NEXT: .reg .b16 %rs<7>;
403 ; CHECK-NEXT: .reg .b16 %rs<
[all...]
H A Dstore-retval.ll48 …; CHECK-NOT: st.param.v4.b8 [func_retval0+20], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
65 …; CHECK-NOT: st.param.v4.b8 [func_retval0+20], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
66 …; CHECK-NOT: st.param.v4.b8 [func_retval0+24], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
67 …; CHECK-NOT: st.param.v4.b8 [func_retval0+28], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
H A Dunaligned-param-load-store.ll25 ; CHECK-DAG: ld.param.u16 [[P0:%rs[0-9]+]], [test_s_i8i16p_param_0];
26 ; CHECK-DAG: ld.param.u8 [[P2_0:%rs[0-9]+]], [test_s_i8i16p_param_0+3];
27 ; CHECK-DAG: ld.param.u8 [[P2_1:%rs[0-9]+]], [test_s_i8i16p_param_0+4];
28 ; CHECK-DAG: shl.b16 [[P2_1_shl:%rs[0-9]+]], [[P2_1]], 8;
29 ; CHECK-DAG: or.b16 [[P2_1_or:%rs[0-9]+]], [[P2_1_shl]], [[P2_0]];
41 ; CHECK-DAG: ld.param.b16 [[R0:%rs[0-9]+]], [retval0];
42 ; CHECK-DAG: ld.param.b8 [[R2_0:%rs[0-9]+]], [retval0+3];
43 ; CHECK-DAG: ld.param.b8 [[R2_1:%rs[0-9]+]], [retval0+4];
46 ; CHECK-DAG: shl.b16 [[R2_1_shl:%rs[0-9]+]], [[R2_1]], 8;
47 ; CHECK-DAG: and.b16 [[R2_0_and:%rs[
[all...]
H A Dcompare-int.ll199 ; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
208 ; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
217 ; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
226 ; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
235 ; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[
[all...]
H A Dparam-load-store.ll27 ; CHECK: ld.param.u8 [[A8:%rs[0-9]+]], [test_i1_param_0];
28 ; CHECK: and.b16 [[A:%rs[0-9]+]], [[A8]], 1;
51 ; CHECK: ld.param.u8 [[A8:%rs[0-9]+]], [test_i1s_param_0];
73 ; CHECK-DAG: ld.param.u8 [[E2:%rs[0-9]+]], [test_v3i1_param_0+2];
74 ; CHECK-DAG: ld.param.u8 [[E0:%rs[0-9]+]], [test_v3i1_param_0]
81 ; CHECK-DAG: ld.param.b8 [[RE0:%rs[0-9]+]], [retval0];
82 ; CHECK-DAG: ld.param.b8 [[RE2:%rs[0-9]+]], [retval0+2];
94 ; CHECK: ld.param.u8 [[E0:%rs[0-9]+]], [test_v4i1_param_0]
100 ; CHECK: ld.param.b8 [[RE0:%rs[0-9]+]], [retval0];
101 ; CHECK: ld.param.b8 [[RE1:%rs[
[all...]
/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td232 let rs = 1;
237 let rs = 0;
258 def Br : I16rr<0b0100, (outs), (ins GR16:$rs),
259 "br\t$rs",
260 [(brind GR16:$rs)]>;
288 (outs), (ins GR16:$rs),
289 "call\t$rs", [(MSP430call GR16:$rs)]>;
293 def CALLn : II16n<0b101, (outs), (ins indreg:$rs), "call\t$rs", []>;
[all...]
/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsDSPInstrFormats.td26 bits<5> rs;
31 let Inst{20-16} = rs;
38 bits<5> rs;
42 let Inst{20-16} = rs;
49 bits<5> rs;
54 let Inst{20-16} = rs;
62 bits<5> rs;
67 let Inst{20-16} = rs;
75 bits<5> rs;
80 let Inst{20-16} = rs;
[all …]
H A DMips64InstrInfo.td409 (ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, uimm5_plus1:$size),
410 "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,
414 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
456 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
457 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
458 let TwoOperandAliasConstraint = "$rd = $rs";
463 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1),
464 !strconcat(opstr, "\t$rt, $rs, $pos, $lenm1"),
465 [(set RO:$rt, (Op RO:$rs, PosIm
[all...]
H A DMicroMipsInstrFormats.td59 bits<3> rs;
66 let Inst{3-1} = rs;
72 bits<3> rs;
79 let Inst{6-4} = rs;
85 bits<3> rs;
92 let Inst{2-0} = rs;
111 bits<3> rs;
118 let Inst{6-4} = rs;
180 bits<5> rs;
187 let Inst{4-0} = rs;
[all …]
H A DMicroMips32r6InstrFormats.td47 bits<3> rs;
53 let Inst{9-7} = rs;
58 bits<5> rs;
63 let Inst{9-5} = rs;
69 bits<5> rs;
76 let Inst{20-16} = rs;
82 bits<5> rs;
89 let Inst{20-16} = rs;
145 bits<5> rs;
151 let Inst{20-16} = rs;
[all …]
H A DMipsInstrFormats.td15 // rs - src reg.
148 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
156 bits<5> rs;
164 let Inst{25-21} = rs;
218 bits<5> rs;
224 let Inst{25-21} = rs;
232 bits<5> rs;
239 let Inst{25-21} = rs;
263 bits<5> rs;
268 let Inst{25-21} = rs;
[all …]
H A DMipsDSPInstrFormats.td67 bits<5> rs;
72 let Inst{25-21} = rs;
81 bits<5> rs;
85 let Inst{25-21} = rs;
94 bits<5> rs;
99 let Inst{25-21} = rs;
107 bits<5> rs;
113 let Inst{25-21} = rs;
121 bits<5> rs;
127 let Inst{25-21} = rs;
[all …]
H A DMipsInstrInfo.td1323 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1324 !strconcat(opstr, "\t$rd, $rs, $rt"),
1325 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1328 let TwoOperandAliasConstraint = "$rd = $rs";
1336 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1337 !strconcat(opstr, "\t$rt, $rs, $imm16"),
1338 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1341 let TwoOperandAliasConstraint = "$rs = $rt";
1346 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1347 !strconcat(opstr, "\t$rs,
[all...]
H A DMips32r6InstrFormats.td178 bits<5> rs;
185 let Inst{25-21} = rs;
284 bits<5> rs;
290 let Inst{25-21} = rs;
296 bits<5> rs;
302 let Inst{25-21} = rs;
308 bits<5> rs;
314 let Inst{25-21} = rs;
351 bits<5> rs;
356 let Inst{25-21} = rs;
[all …]
H A DMicroMipsInstrInfo.td204 InstSE<(outs), (ins RO:$rs, opnd:$offset),
205 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
239 MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),
240 !strconcat(opstr, "\t$rd1, $rd2, $rs, $rt"), [],
308 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
309 !strconcat(opstr, "\t$rd, $rs, $rt"),
310 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
316 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
317 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
322 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
[all …]
/llvm-project/clang/test/Analysis/
H A Dmpichecker.cpp99 ReqStruct rs; in doubleNonblocking3() local
104 MPI_Ireduce(MPI_IN_PLACE, &buf, 1, MPI_DOUBLE, MPI_SUM, 0, MPI_COMM_WORLD, &rs.req); in doubleNonblocking3()
105 …MPI_Ireduce(MPI_IN_PLACE, &buf, 1, MPI_DOUBLE, MPI_SUM, 0, MPI_COMM_WORLD, &rs.req); // expected-w… in doubleNonblocking3()
106 MPI_Wait(&rs.req, MPI_STATUS_IGNORE); in doubleNonblocking3()
141 ReqStruct rs; in missingNonBlocking2() local
142 MPI_Request *r = &rs.req[0][1]; in missingNonBlocking2()
219 ReqStruct rs; in noDoubleRequestUsage() local
225 &rs.req); in noDoubleRequestUsage()
227 &rs.req2); in noDoubleRequestUsage()
228 MPI_Wait(&rs.req, MPI_STATUS_IGNORE); in noDoubleRequestUsage()
[all …]
H A DMemRegion.cpp25 ReqStruct rs; in testGetDescriptiveName3() local
26 MPI_Request *r = &rs.req; in testGetDescriptiveName3()
34 ReqStruct rs; in testGetDescriptiveName4() local
35 MPI_Request *r = &rs.req[0][1]; in testGetDescriptiveName4()
44 ReqStruct rs; in testGetDescriptiveName5() local
45 MPI_Request *r = &rs.req.req; in testGetDescriptiveName5()
/llvm-project/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-xlcompat-rotate.c75 unsigned int testrotatel4(unsigned int rs, unsigned int shift) { in testrotatel4() argument
76 return __rotatel4(rs, shift); in testrotatel4()
83 unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) { in testrotatel8() argument
84 return __rotatel8(rs, shift); in testrotatel8()
92 unsigned long long testrdlam(unsigned long long rs, unsigned int shift) { in testrdlam() argument
95 return __rdlam(rs, shift, 7); in testrdlam()

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