Home
last modified time | relevance | path

Searched refs:contract (Results 1 – 25 of 519) sorted by relevance

12345678910>>...21

/llvm-project/llvm/test/CodeGen/X86/
H A Dpr46877.ll206 %81 = fsub reassoc nsz contract float %0, %1
207 %82 = fmul reassoc nsz contract float %1, %2
208 %83 = fmul reassoc nsz contract float %3, %82
209 %84 = fsub reassoc nsz contract float %0, %83
210 %85 = fmul reassoc nsz contract float %84, %4
211 %86 = fmul reassoc nsz contract float %81, %5
212 %87 = fsub reassoc nsz contract float %0, %86
213 %88 = fmul reassoc nsz contract float %87, %85
214 %89 = fmul reassoc nsz contract float %81, %6
215 %90 = fmul reassoc nsz contract floa
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dhigh-RP-reschedule.mir54 %29:vreg_64 = contract nofpexcept V_MUL_F64_e64 0, %7.sub2_sub3, 0, %25.sub2_sub3, 0, 0, implicit $mode, implicit $exec
55 %30:vreg_64 = contract nofpexcept V_MUL_F64_e64 0, %7.sub2_sub3, 0, %25.sub0_sub1, 0, 0, implicit $mode, implicit $exec
56 %31:vreg_64 = contract nofpexcept V_FMA_F64_e64 0, %7.sub0_sub1, 0, %25.sub0_sub1, 1, %29, 0, 0, implicit $mode, implicit $exec
57 %32:vreg_64 = contract nofpexcept V_FMA_F64_e64 0, %7.sub0_sub1, 0, %25.sub2_sub3, 0, %30, 0, 0, implicit $mode, implicit $exec
58 %33:vreg_64 = contract nofpexcept V_MUL_F64_e64 0, %5.sub2_sub3, 0, %24.sub2_sub3, 0, 0, implicit $mode, implicit $exec
59 %34:vreg_64 = contract nofpexcept V_MUL_F64_e64 0, %5.sub2_sub3, 0, %24.sub0_sub1, 0, 0, implicit $mode, implicit $exec
60 %35:vreg_64 = contract nofpexcept V_FMA_F64_e64 0, %5.sub0_sub1, 0, %24.sub0_sub1, 1, %33, 0, 0, implicit $mode, implicit $exec
61 %36:vreg_64 = contract nofpexcept V_FMA_F64_e64 0, %5.sub0_sub1, 0, %24.sub2_sub3, 0, %34, 0, 0, implicit $mode, implicit $exec
62 %37:vreg_64 = contract nofpexcept V_MUL_F64_e64 0, %9.sub2_sub3, 0, %28.sub2_sub3, 0, 0, implicit $mode, implicit $exec
63 %38:vreg_64 = contract nofpexcep
[all...]
H A Dfold-fabs.ll19 %0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
20 %1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
21 %2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
22 %3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
27 %if.3 = fmul reassoc nnan nsz arcp contract afn float %2, 0x3FC99999A0000000
52 %0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
53 %1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
54 %2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
55 %3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
60 %if.3 = fmul reassoc nnan nsz arcp contract afn float %2, 0x3FC99999A0000000
[all …]
H A Dllvm.amdgcn.iglp.opt.exp.large.mir1238 early-clobber %668:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_vgprcd_e64 %612.sub0_sub1:vreg_128_align2, %391.sub0_sub1:vreg_128_align2, 0, 0, 0, 0, implicit $mode, implicit $exec
1239 %668:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %612.sub2_sub3:vreg_128_align2, %391.sub2_sub3:vreg_128_align2, %668:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
1241 early-clobber %679:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_vgprcd_e64 %626.sub0_sub1:vreg_128_align2, %391.sub0_sub1:vreg_128_align2, 0, 0, 0, 0, implicit $mode, implicit $exec
1242 %679:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %626.sub2_sub3:vreg_128_align2, %391.sub2_sub3:vreg_128_align2, %679:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
1244 early-clobber %690:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_vgprcd_e64 %638.sub0_sub1:vreg_128_align2, %391.sub0_sub1:vreg_128_align2, 0, 0, 0, 0, implicit $mode, implicit $exec
1245 %690:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %638.sub2_sub3:vreg_128_align2, %391.sub2_sub3:vreg_128_align2, %690:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
1247 early-clobber %701:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_vgprcd_e64 %650.sub0_sub1:vreg_128_align2, %391.sub0_sub1:vreg_128_align2, 0, 0, 0, 0, implicit $mode, implicit $exec
1248 %701:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %650.sub2_sub3:vreg_128_align2, %391.sub2_sub3:vreg_128_align2, %701:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
1250 %668:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %662.sub0_sub1:vreg_128_align2, %392.sub0_sub1:vreg_128_align2, %668:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
1251 %668:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e6
[all...]
H A Dllvm.amdgcn.iglp.opt.exp.small.mir558 early-clobber %43:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_vgprcd_e64 %41.sub0_sub1:vreg_128_align2, %44.sub0_sub1:vreg_128_align2, 0, 0, 0, 0, implicit $mode, implicit $exec
559 %43:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %41.sub2_sub3:vreg_128_align2, %44.sub2_sub3:vreg_128_align2, %43:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
561 early-clobber %46:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_vgprcd_e64 %45.sub0_sub1:vreg_128_align2, %44.sub0_sub1:vreg_128_align2, 0, 0, 0, 0, implicit $mode, implicit $exec
562 %46:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %45.sub2_sub3:vreg_128_align2, %44.sub2_sub3:vreg_128_align2, %46:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
564 %43:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %47.sub0_sub1:vreg_128_align2, %49.sub0_sub1:vreg_128_align2, %43:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
565 %43:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %47.sub2_sub3:vreg_128_align2, %49.sub2_sub3:vreg_128_align2, %43:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
567 %46:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %50.sub0_sub1:vreg_128_align2, %49.sub0_sub1:vreg_128_align2, %46:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
568 %46:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %50.sub2_sub3:vreg_128_align2, %49.sub2_sub3:vreg_128_align2, %46:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
573 %43:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e64 %51.sub0_sub1:vreg_128_align2, %52.sub0_sub1:vreg_128_align2, %43:vreg_512_align2, 0, 0, 0, implicit $mode, implicit $exec
574 %43:vreg_512_align2 = contract V_MFMA_F32_32X32X8F16_mac_vgprcd_e6
[all...]
H A Ddagcombine-fma-crash.ll24 …; CHECK-NEXT: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 0…
25 …; CHECK-NEXT: [[V_FMAC_F32_e64_1:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 …
26 …; CHECK-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_ADD_F32_e64 0, …
51 %i = fadd reassoc contract float 0.000000e+00, 0.000000e+00
56 %i3 = fmul reassoc contract float %i, %i
57 %i4 = fmul reassoc contract float %arg, %arg
58 %i5 = fadd reassoc contract float %i3, 1.000000e+00
59 %i6 = fadd reassoc contract float %i5, %i4
60 %i7 = fmul reassoc contract float %arg, %arg
61 %i8 = fmul reassoc contract float %i, %i
[all …]
H A Damdgpu-simplify-libcall-sincos.nobuiltins.ll17 ; CHECK-NEXT: [[TMP0:%.*]] = call contract float @_Z6sincosfPU3AS5f(float [[X]], ptr addrspace(5) [[__SINCOS_]])
20 ; CHECK-NEXT: [[CALL1:%.*]] = tail call contract float @_Z3cosf(float noundef [[X]])
25 %call = tail call contract float @_Z3sinf(float noundef %x)
27 %call1 = tail call contract float @_Z3cosf(float noundef %x)
38 ; CHECK-NEXT: [[TMP0:%.*]] = call contract <2 x float> @_Z6sincosDv2_fPU3AS5S_(<2 x float> [[X]], ptr addrspace(5) [[__SINCOS_]])
41 ; CHECK-NEXT: [[CALL1:%.*]] = tail call contract <2 x float> @_Z3cosDv2_f(<2 x float> noundef [[X]])
46 %call = tail call contract <2 x float> @_Z3sinDv2_f(<2 x float> noundef %x)
48 %call1 = tail call contract <2 x float> @_Z3cosDv2_f(<2 x float> noundef %x)
58 ; CHECK-NEXT: [[TMP0:%.*]] = call contract float @_Z6sincosfPU3AS5f(float [[X]], ptr addrspace(5) [[__SINCOS_]])
61 ; CHECK-NEXT: [[CALL1:%.*]] = tail call contract floa
[all...]
H A Damdgpu-simplify-libcall-sincos.ll92 ; CHECK-NEXT: [[CALL:%.*]] = tail call contract half @_Z3sinDh(half [[X]])
94 ; CHECK-NEXT: [[CALL1:%.*]] = tail call contract half @_Z3cosDh(half [[X]])
99 %call = tail call contract half @_Z3sinDh(half %x)
101 %call1 = tail call contract half @_Z3cosDh(half %x)
110 ; CHECK-NEXT: [[CALL1:%.*]] = tail call contract half @_Z3cosDh(half [[X]])
112 ; CHECK-NEXT: [[CALL:%.*]] = tail call contract half @_Z3sinDh(half [[X]])
117 %call1 = tail call contract half @_Z3cosDh(half %x)
119 %call = tail call contract half @_Z3sinDh(half %x)
128 ; CHECK-NEXT: [[CALL:%.*]] = tail call contract <2 x half> @_Z3sinDv2_Dh(<2 x half> [[X]])
130 ; CHECK-NEXT: [[CALL1:%.*]] = tail call contract <
[all...]
/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/
H A Drcp-contract-rsq.ll25 ; CHECK-NEXT: [[RSQ:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[X]])
28 %sqrt = call contract float @llvm.amdgcn.sqrt.f32(float %x)
29 %rsq = call contract float @llvm.amdgcn.rcp.f32(float %sqrt)
33 ; contract required on both calls
38 ; CHECK-NEXT: [[RSQ:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[SQRT]])
42 %rsq = call contract float @llvm.amdgcn.rcp.f32(float %sqrt)
46 ; contract required on both calls
50 ; CHECK-NEXT: [[SQRT:%.*]] = call contract float @llvm.amdgcn.sqrt.f32(float [[X]])
54 %sqrt = call contract float @llvm.amdgcn.sqrt.f32(float %x)
63 ; CHECK-NEXT: [[SQRT:%.*]] = call contract float @llvm.amdgcn.sqrt.f32(float [[X]])
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dcomplex-deinterleaving-add-mull-fixed-contract.ll29 %0 = fmul contract <2 x double> %strided.vec, %strided.vec31
30 %1 = fmul contract <2 x double> %strided.vec28, %strided.vec30
31 %2 = fadd contract <2 x double> %1, %0
32 %3 = fmul contract <2 x double> %strided.vec, %strided.vec30
33 %4 = fmul contract <2 x double> %strided.vec28, %strided.vec31
34 %5 = fsub contract <2 x double> %3, %4
37 %6 = fadd contract <2 x double> %strided.vec33, %5
38 %7 = fadd contract <2 x double> %2, %strided.vec34
67 %0 = fmul contract <2 x double> %strided.vec, %strided.vec54
68 %1 = fmul contract <2 x double> %strided.vec51, %strided.vec53
[all …]
H A Dcomplex-deinterleaving-add-mull-scalable-contract.ll34 %4 = fmul contract <vscale x 2 x double> %0, %3
35 %5 = fmul contract <vscale x 2 x double> %1, %2
36 %6 = fadd contract <vscale x 2 x double> %5, %4
37 %7 = fmul contract <vscale x 2 x double> %0, %2
38 %8 = fmul contract <vscale x 2 x double> %1, %3
39 %9 = fsub contract <vscale x 2 x double> %7, %8
43 %12 = fadd contract <vscale x 2 x double> %10, %9
44 %13 = fadd contract <vscale x 2 x double> %6, %11
76 %4 = fmul contract <vscale x 2 x double> %0, %3
77 %5 = fmul contract <vscale x 2 x double> %1, %2
[all …]
H A Dsve-fp-combine.ll9 %mul = fmul contract <vscale x 8 x half> %m1, %m2
10 %add = fadd contract <vscale x 8 x half> %acc, %mul
20 %mul = fmul contract <vscale x 4 x half> %m1, %m2
21 %add = fadd contract <vscale x 4 x half> %acc, %mul
31 %mul = fmul contract <vscale x 2 x half> %m1, %m2
32 %add = fadd contract <vscale x 2 x half> %acc, %mul
42 %mul = fmul contract <vscale x 4 x float> %m1, %m2
43 %add = fadd contract <vscale x 4 x float> %acc, %mul
53 %mul = fmul contract <vscale x 2 x float> %m1, %m2
54 %add = fadd contract <vscale x 2 x float> %acc, %mul
[all …]
H A Dneon-fma-FMF.ll7 %tmp1 = fmul contract <2 x float> %A, %B;
8 %tmp2 = fadd contract <2 x float> %C, %tmp1;
13 ; the contract on the fadd
18 %tmp2 = fadd contract <2 x float> %C, %tmp1;
26 %tmp1 = fmul contract <2 x float> %A, %B;
34 %tmp1 = fmul contract <2 x float> %A, %B;
35 %tmp2 = fsub contract <2 x float> %C, %tmp1;
40 ; the contract on the fsub
45 %tmp2 = fsub contract <2 x float> %C, %tmp1;
53 %tmp1 = fmul contract <2 x float> %A, %B;
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dfma-precision.ll14 %mul = fmul contract reassoc double %b, %a
15 %mul1 = fmul contract reassoc double %d, %c
16 %sub = fsub contract reassoc nsz double %mul, %mul1
17 %mul3 = fmul contract reassoc double %mul, %sub
31 %mul = fmul contract reassoc double %b, %a
32 %mul1 = fmul contract reassoc double %d, %c
33 %sub = fsub contract reassoc double %mul, %mul1
34 %mul3 = fmul contract reassoc double %mul1, %sub
47 %mul = fmul contract reassoc double %b, %a
48 %mul1 = fmul contract reassoc double %d, %c
[all …]
H A Dmachine-combiner.ll211 %7 = fmul contract reassoc nsz double %3, %2
212 %8 = fmul contract reassoc nsz double %5, %4
213 %9 = fadd contract reassoc nsz double %1, %0
214 %10 = fadd contract reassoc nsz double %9, %7
215 %11 = fadd contract reassoc nsz double %10, %8
226 %7 = fmul contract reassoc nsz float %3, %2
227 %8 = fmul contract reassoc nsz float %5, %4
228 %9 = fadd contract reassoc nsz float %1, %0
229 %10 = fadd contract reassoc nsz float %9, %7
230 %11 = fadd contract reassoc nsz float %10, %8
[all …]
H A Dfma-negate.ll20 %0 = fmul contract reassoc double %b, %c
21 %1 = fsub contract reassoc double %a, %0
39 %0 = fmul contract reassoc double %a, %b
40 %1 = fmul contract reassoc double %c, %d
41 %2 = fsub contract reassoc double %0, %1
59 %0 = fsub contract reassoc double -0.0, %a
60 %1 = call contract reassoc double @llvm.fma.f64(double %0, double %b,
78 %0 = fmul contract reassoc float %b, %c
79 %1 = fsub contract reassoc float %a, %0
97 %0 = fmul contract reasso
[all...]
/llvm-project/mlir/test/Conversion/ComplexToStandard/
H A Dconvert-to-standard.mlir227 %expm1 = complex.expm1 %arg fastmath<nnan,contract> : complex<f32>
234 // CHECK: %[[EXPM1:.*]] = math.expm1 %[[REAL]] fastmath<nnan,contract> : f32
235 // CHECK: %[[VAL_6:.*]] = arith.addf %[[EXPM1]], %[[C1_F32]] fastmath<nnan,contract> : f32
236 // CHECK: %[[VAL_7:.*]] = math.sin %[[IMAG]] fastmath<nnan,contract> : f32
239 // CHECK: %[[VAL_10:.*]] = math.cos %[[IMAG]] fastmath<nnan,contract> : f32
240 // CHECK: %[[VAL_11:.*]] = arith.addf %[[VAL_10]], %[[VAL_9]] fastmath<nnan,contract> : f32
241 // CHECK: %[[VAL_12:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] fastmath<nnan,contract> : f32
242 // CHECK: %[[VAL_13:.*]] = arith.mulf %[[VAL_12]], %[[VAL_12]] fastmath<nnan,contract> : f32
245 // CHECK: %[[FMA0:.*]] = math.fma %[[COEF0]], %[[VAL_12]], %[[COEF1]] fastmath<nnan,contract> : f32
247 // CHECK: %[[FMA1:.*]] = math.fma %[[FMA0]], %[[VAL_12]], %[[COEF2]] fastmath<nnan,contract>
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-fdiv-sqrt-to-rsq.mir16 ; GCN-NEXT: [[INT:%[0-9]+]]:_(s16) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %x(s16)
21 %sqrt:_(s16) = contract G_FSQRT %x
23 %rsq:_(s16) = contract G_FDIV %one, %sqrt
43 ; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
50 %rsq:_(s16) = contract G_FDIV %one, %sqrt
68 ; GCN-NEXT: %sqrt:_(s16) = contract G_FSQRT %x
75 %sqrt:_(s16) = contract G_FSQRT %x
95 ; GCN-NEXT: [[INT:%[0-9]+]]:_(s16) = contract G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %x(s16)
96 ; GCN-NEXT: %rsq:_(s16) = contract G_FNEG [[INT]]
101 %sqrt:_(s16) = contract G_FSQRT %x
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dpow.75.ll32 ; CHECK: Combining: [[FIRST]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], Co…
33 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
34 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn …
35 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc …
36 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
37 ; CHECK: Combining: [[SECOND]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], C…
38 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
39 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn …
40 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc …
41 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dmachine-combiner-reassoc-fp.ll25 %add = fadd reassoc nsz arcp contract afn double %1, %0
28 %add3 = fadd reassoc nsz arcp contract afn double %add, %2
31 %add5 = fadd reassoc nsz arcp contract afn double %add3, %3
34 %add7 = fadd reassoc nsz arcp contract afn double %add5, %4
37 %add9 = fadd reassoc nsz arcp contract afn double %add7, %5
40 %add11 = fadd reassoc nsz arcp contract afn double %add9, %6
43 %add13 = fadd reassoc nsz arcp contract afn double %add11, %7
65 %add = fadd reassoc nsz arcp contract afn float %1, %0
68 %add3 = fadd reassoc nsz arcp contract afn float %add, %2
71 %add5 = fadd reassoc nsz arcp contract afn float %add3, %3
[all …]
/llvm-project/clang/test/Headers/
H A D__clang_hip_math.hip262 // DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acos_f32(float noundef [[X:%.*]]) #[[ATTR12:[0-9]+]]
267 // FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_acos_f32(float noundef nofpclass(nan inf) [[X:%.*]]) #[[ATTR12:[0-9]+]]
272 // APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acos_f32(float noundef [[X:%.*]]) #[[ATTR12:[0-9]+]]
281 // DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_acos_f64(double noundef [[X:%.*]]) #[[ATTR12]]
286 // FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_acos_f64(double noundef nofpclass(nan inf) [[X:%.*]]) #[[ATTR12]]
291 // APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_acos_f64(double noundef [[X:%.*]]) #[[ATTR12]]
300 // DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acosh_f32(float noundef [[X:%.*]]) #[[ATTR13:[0-9]+]]
305 // FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_acosh_f32(float noundef nofpclass(nan inf) [[X:%.*]]) #[[ATTR13:[0-9]+]]
310 // APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acosh_f32(float noundef [[X:%.*]]) #[[ATTR13:[0-9]+]]
319 // DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract nounde
[all...]
H A D__clang_hip_math_ocml_rounded_ops.hip12 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_add_rtn_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR3:[0-9]+]]
21 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_add_rte_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR3]]
30 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_add_rtp_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR3]]
39 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_add_rtz_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR3]]
48 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fma_rtn_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR3]]
57 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fma_rte_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR3]]
66 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fma_rtp_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR3]]
75 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fma_rtz_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR3]]
84 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_mul_rtn_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR3]]
93 // CHECK-NEXT: [[CALL_I:%.*]] = tail call contract nounde
[all...]
/llvm-project/clang/test/CodeGen/
H A Dfp-contract-fast-pragma.cpp17 #pragma clang fp contract(fast) in fp_contract_1()
29 #pragma clang fp contract(fast) in fp_contract_2()
40 #pragma clang fp contract(fast) in template_muladd()
56 #pragma clang fp contract(fast) in method()
69 #pragma clang fp contract(fast)
80 #pragma clang fp contract(fast) contract(off)
91 #pragma clang fp contract(fast)
103 #pragma clang fp contract(off) in fp_contract_8()
/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
H A Dfused_costs.ll2 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
3 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=on < %s | FileChe…
4 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=fast < %s | FileC…
5 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
7 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
8 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=on < %s | FileChe…
9 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=fast < %s | FileC…
10 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
19 ; SLOWF32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32c = fmul contract fl…
20 ; SLOWF32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32cadd = fadd contract…
[all …]
/llvm-project/mlir/test/Dialect/Arith/
H A Demulate-unsupported-floats.mlir7 // CHECK-DAG: [[X_EXP:%.+]] = arith.extf [[X]] fastmath<contract> : bf16 to f32
8 // CHECK-DAG: [[C_EXP:%.+]] = arith.extf [[C]] fastmath<contract> : bf16 to f32
10 // CHECK: [[Y:%.+]] = arith.truncf [[Y_EXP]] fastmath<contract> : f32 to bf16
22 // CHECK-DAG: [[X_EXP:%.+]] = arith.extf [[X]] fastmath<contract> : bf16 to f32
23 // CHECK-DAG: [[Y_EXP:%.+]] = arith.extf [[Y]] fastmath<contract> : bf16 to f32
24 // CHECK-DAG: [[Z_EXP:%.+]] = arith.extf [[Z]] fastmath<contract> : bf16 to f32
26 // CHECK: [[P:%.+]] = arith.truncf [[P_EXP]] fastmath<contract> : f32 to bf16
27 // CHECK: [[P_EXP2:%.+]] = arith.extf [[P]] fastmath<contract> : bf16 to f32
29 // CHECK: [[Q:%.+]] = arith.truncf [[Q_EXP]] fastmath<contract> : f32 to bf16
30 // CHECK: [[Q_EXP2:%.+]] = arith.extf [[Q]] fastmath<contract> : bf16 to f32
[all …]

12345678910>>...21