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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td12 bits <5> Vu32;
14 bits <5> Rt32;
16 bits <5> Vdd32;
20 bits <7> Ii;
22 bits <5> Rs32;
24 bits <2> Pd4;
28 bits <5> Rss32;
30 bits <5> Rt32;
32 bits <2> Pd4;
36 bits <11> Ii;
[all …]
/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
61 bits<16> Inst;
70 class ANDI_FM_MM16<bits<6> funct> {
71 bits<3> rd;
72 bits<3> rs;
[all …]
H A DMicroMips32r6InstrFormats.td38 bits<10> offset;
40 bits<16> Inst;
46 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
47 bits<3> rs;
48 bits<7> offset;
50 bits<16> Inst;
57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
60 bits<16> Inst;
68 bits<5> rt;
[all …]
H A DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
H A DMipsInstrFormats.td26 class Format<bits<4> val> {
27 bits<4> Value = val;
74 field bits<32> Inst;
81 bits<6> Opcode = 0;
83 // Top 6 bits are the 'opcode' field
96 bits<4> FormBits = Form.Value;
111 field bits<32> SoftFail = 0;
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
155 bits<5> rd;
156 bits<5> rs;
[all …]
H A DMicroMipsDSPInstrFormats.td24 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
36 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
37 bits<5> rt;
38 bits<5> rs;
47 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
48 bits<5> rt;
49 bits<5> rs;
[all …]
H A DMips32r6InstrFormats.td43 class OPGROUP<bits<6> Val> {
44 bits<6> Value = Val;
65 class OPCODE2<bits<2> Val> {
66 bits<2> Value = Val;
72 class OPCODE3<bits<3> Val> {
73 bits<3> Value = Val;
77 class OPCODE5<bits<5> Val> {
78 bits<5> Value = Val;
98 class OPCODE6<bits<6> Val> {
99 bits<6> Value = Val;
[all …]
H A DMipsDSPInstrFormats.td39 class Field6<bits<6> val> {
40 bits<6> V = val;
65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 bits<5> rd;
81 bits<5> rs;
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
[all …]
H A DMips16InstrFormats.td58 field bits<16> Inst;
59 bits<5> Opcode = 0;
61 // Top 5 bits are the 'opcode' field
65 field bits<16> SoftFail = 0;
75 field bits<32> Inst;
78 field bits<32> SoftFail = 0;
102 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
106 bits<11> imm11;
117 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
121 bits<3> rx;
[all …]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
77 field bits<32> Word0;
79 bits<11> src0;
80 bits<1> src0_rel;
81 bits<11> src1;
82 bits<1> src1_rel;
83 bits<3> index_mode = 0;
84 bits<2> pred_sel;
85 bits<1> last;
[all …]
/llvm-project/llvm/test/TableGen/
H A DBitsInit.td5 bits<2> opc = { 0, 1 };
6 bits<2> opc2 = { 1, 0 };
7 bits<1> opc3 = { 1 };
8 bits<2> b = { opc{0}, opc2{0} };
9 bits<2> c = { opc{1}, opc2{1} };
10 bits<2> c = { opc3{0}, opc3 };
14 // CHECK: bits<2> opc = { 0, 1 };
15 // CHECK: bits<2> opc2 = { 1, 0 };
16 // CHECK: bits<1> opc3 = { 1 };
17 // CHECK: bits<
[all...]
H A Darithmetic.td7 // CHECK: bits<8> add = { 0, 0, 0, 1, 1, 0, 0, 0 };
8 // CHECK: bits<8> sub = { 0, 0, 0, 1, 0, 0, 1, 0 };
9 // CHECK: bits<8> and = { 0, 0, 0, 0, 0, 0, 0, 1 };
10 // CHECK: bits<8> or = { 0, 0, 0, 1, 0, 1, 1, 1 };
11 // CHECK: bits<8> xor = { 0, 0, 0, 1, 0, 1, 1, 0 };
12 // CHECK: bits<8> srl = { 0, 0, 0, 0, 0, 0, 1, 0 };
13 // CHECK: bits<8> sra = { 0, 0, 0, 0, 0, 0, 1, 0 };
14 // CHECK: bits<8> shl = { 1, 0, 1, 0, 1, 0, 0, 0 };
16 // CHECK: bits<8> sra = { 1, 1, 1, 1, 1, 1, 1, 1 };
18 class A<bits<8> a, bits<2> b> {
[all …]
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
15 field bits<32> Inst;
16 field bits<32> SoftFail = 0;
28 bits<1> PPC970_First = 0;
29 bits<1> PPC970_Single = 0;
30 bits<1> PPC970_Cracked = 0;
31 bits<3> PPC970_Unit = 0;
41 bits<1> XFormMemOp = 0;
45 bits<1> Prefixed = 0;
49 // 32 bits t
[all...]
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td16 field bits<16> Inst;
21 field bits<16> SoftFail = 0;
25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
28 bits<5> rs1;
29 bits<5> rs2;
38 // is responsible for setting the appropriate bits in the Inst field.
39 // The bits Inst{12} and Inst{6-2} may need to be set differently for some
41 class RVInst16CI<bits<3> funct3, bits<
[all...]
/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrFormats.td21 class Fmt1RI13_XI<bits<32> op, dag outs, dag ins, string opnstr,
24 bits<13> imm13;
25 bits<5> xd;
34 class Fmt2R_XX<bits<32> op, dag outs, dag ins, string opnstr,
37 bits<5> xj;
38 bits<5> xd;
46 class Fmt2R_XR<bits<32> op, dag outs, dag ins, string opnstr,
49 bits<5> rj;
50 bits<5> xd;
58 class Fmt2R_CX<bits<32> op, dag outs, dag ins, string opnstr,
[all …]
H A DLoongArchLSXInstrFormats.td21 class Fmt1RI13_VI<bits<32> op, dag outs, dag ins, string opnstr,
24 bits<13> imm13;
25 bits<5> vd;
34 class Fmt2R_VV<bits<32> op, dag outs, dag ins, string opnstr,
37 bits<5> vj;
38 bits<5> vd;
46 class Fmt2R_VR<bits<32> op, dag outs, dag ins, string opnstr,
49 bits<5> rj;
50 bits<5> vd;
58 class Fmt2R_CV<bits<32> op, dag outs, dag ins, string opnstr,
[all …]
H A DLoongArchInstrFormats.td22 field bits<32> Inst;
27 field bits<32> SoftFail = 0;
59 class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr,
62 bits<5> rj;
63 bits<5> rd;
72 class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr,
75 bits<5> rk;
76 bits<5> rj;
77 bits<5> rd;
87 class Fmt3RI2<bits<3
[all...]
/llvm-project/clang/test/Sema/
H A Dbittest-intrinsics.c11 void x86(long *bits, __int64 *bits64, long bitidx) { in x86() argument
12 sink = _bittest(bits, bitidx); in x86()
13 sink = _bittestandcomplement(bits, bitidx); in x86()
14 sink = _bittestandreset(bits, bitidx); in x86()
15 sink = _bittestandset(bits, bitidx); in x86()
16 sink = _interlockedbittestandreset(bits, bitidx); in x86()
17 sink = _interlockedbittestandset(bits, bitidx); in x86()
26 …sink = _interlockedbittestandreset_acq(bits, bitidx); // expected-error {{builtin is not supported… in x86()
27 …sink = _interlockedbittestandreset_rel(bits, bitidx); // expected-error {{builtin is not supported… in x86()
28 …sink = _interlockedbittestandreset_nf(bits, bitidx); // expected-error {{builtin is not supported … in x86()
[all …]
/llvm-project/libc/test/utils/FPUtil/
H A Dx86_long_double_test.cpp24 FPBits bits(0.0l); in TEST() local
25 bits.set_biased_exponent(FPBits::MAX_BIASED_EXPONENT); in TEST()
29 bits.set_mantissa(i); in TEST()
30 ASSERT_TRUE(bits.is_nan()); in TEST()
33 bits.set_implicit_bit(1); in TEST()
38 bits.set_mantissa(i); in TEST()
39 ASSERT_TRUE(bits.is_nan()); in TEST()
42 bits.set_biased_exponent(1); in TEST()
43 bits.set_implicit_bit(0); in TEST()
47 bits in TEST()
[all...]
/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td32 field bits<24> Inst;
33 field bits<24> SoftFail = 0;
40 field bits<16> Inst;
41 field bits<16> SoftFail = 0;
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
48 bits<4> r;
49 bits<4> s;
50 bits<4> t;
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
63 bits<4> r;
[all …]
/llvm-project/clang/test/Analysis/
H A Dfields.c62 struct Bits bits; in testBitfields() local
64 if (foo() && bits.b) // expected-warning {{garbage}} in testBitfields()
66 if (foo() && bits.inner.e) // expected-warning {{garbage}} in testBitfields()
69 bits.c = 1; in testBitfields()
70 clang_analyzer_eval(bits.c == 1); // expected-warning {{TRUE}} in testBitfields()
72 if (foo() && bits.b) // expected-warning {{garbage}} in testBitfields()
74 if (foo() && bits.x) // expected-warning {{garbage}} in testBitfields()
77 bits.x = true; in testBitfields()
78 clang_analyzer_eval(bits.x == true); // expected-warning{{TRUE}} in testBitfields()
79 bits.b = 2; in testBitfields()
[all …]
/llvm-project/llvm/lib/Target/VE/
H A DVEInstrFormats.td25 field bits<64> Inst;
30 bits<8> op;
38 bits<1> VE_Vector = 0;
39 bits<1> VE_VLInUse = 0;
40 bits<3> VE_VLIndex = 0;
41 bits<1> VE_VLWithMask = 0;
58 field bits<64> SoftFail = 0;
68 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
70 bits<1> cx = 0;
71 bits<7> sx;
[all …]
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td9 class AddrMode<bits<5> val> {
10 bits<5> Value = val;
27 field bits<32> SoftFail = 0;
42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
45 field bits<32> Inst;
51 field bits<16> Inst;
57 class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
60 bits<26> offset;
68 class I_18_Z_L<bits<3> sop, string asm, dag outs, dag ins, list<dag> pattern>
70 bits<5> rz;
[all …]
H A DCSKYInstrFormats16Instr.td9 class J16<bits<5> sop, string opstr, dag ins>
12 bits<10> offset;
18 class J16_B<bits<5> sop, string opstr>
21 bits<10> offset;
27 class R16_XYZ<bits<2> sop, string opstr, SDNode opnode> : CSKY16Inst<AddrModeNone,
30 bits<3> rz;
31 bits<3> rx;
32 bits<3> ry;
40 class R16_XZ_BINOP<bits<4> op, bits<2> sop, string opstr, PatFrag opnode> : CSKY16Inst<
43 bits<4> rz;
[all …]
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td12 field bits<32> Inst;
17 bits<2> op;
18 let Inst{31-30} = op; // Top two bits are the 'op' field
26 field bits<32> SoftFail = 0;
39 bits<3> op2;
40 bits<22> imm22;
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
51 bits<5> rd;
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
61 bits<4> cond;
[all …]

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