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/llvm-project/llvm/test/CodeGen/AVR/
H A Dbranch-relaxation-long.ll
H A Djmp-long.ll14 tail call addrspace(0) void asm sideeffect "nop", ""()
15 tail call addrspace(0) void asm sideeffect "nop", ""()
16 tail call addrspace(0) void asm sideeffect "nop", ""()
17 tail call addrspace(0) void asm sideeffect "nop", ""()
18 tail call addrspace(0) void asm sideeffect "nop", ""()
19 tail call addrspace(0) void asm sideeffect "nop", ""()
20 tail call addrspace(0) void asm sideeffect "nop", ""()
21 tail call addrspace(0) void asm sideeffect "nop", ""()
22 tail call addrspace(0) void asm sideeffect "nop", ""()
23 tail call addrspace(0) void asm sideeffect "nop", ""()
[all …]
H A Dbranch-relaxation.ll26 call void asm sideeffect "nop", ""()
27 call void asm sideeffect "nop", ""()
28 call void asm sideeffect "nop", ""()
29 call void asm sideeffect "nop", ""()
30 call void asm sideeffect "nop", ""()
31 call void asm sideeffect "nop", ""()
32 call void asm sideeffect "nop", ""()
33 call void asm sideeffect "nop", ""()
34 call void asm sideeffect "nop", ""()
35 call void asm sideeffec
[all...]
/llvm-project/llvm/utils/UpdateTestChecks/
H A Dasm.py90 r"(?:^[ \t]+\.(frame|f?mask|set).*?\n)+" # Mips+LLVM standard asm prologue
92 # Mips+LLVM standard asm epilogue
284 def scrub_asm_x86(asm, args):
287 asm = common.SCRUB_WHITESPACE_RE.sub(r" ", asm)
289 asm = string.expandtabs(asm, 2)
291 # Detect shuffle asm comments and hide the operands in favor of the comments.
293 asm = SCRUB_X86_SHUFFLES_NO_MEM_RE.sub(r"\1 {{.*#+}} \2", asm)
278 scrub_asm_x86(asm, args) global() argument
312 scrub_asm_amdgpu(asm, args) global() argument
323 scrub_asm_arm_eabi(asm, args) global() argument
336 scrub_asm_bpf(asm, args) global() argument
347 scrub_asm_hexagon(asm, args) global() argument
358 scrub_asm_powerpc(asm, args) global() argument
373 scrub_asm_m68k(asm, args) global() argument
384 scrub_asm_mips(asm, args) global() argument
395 scrub_asm_msp430(asm, args) global() argument
406 scrub_asm_avr(asm, args) global() argument
417 scrub_asm_riscv(asm, args) global() argument
428 scrub_asm_lanai(asm, args) global() argument
439 scrub_asm_sparc(asm, args) global() argument
450 scrub_asm_spirv(asm, args) global() argument
461 scrub_asm_systemz(asm, args) global() argument
472 scrub_asm_wasm(asm, args) global() argument
483 scrub_asm_ve(asm, args) global() argument
494 scrub_asm_csky(asm, args) global() argument
507 scrub_asm_nvptx(asm, args) global() argument
518 scrub_asm_loongarch(asm, args) global() argument
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dvgpr-agpr-limit-gfx90a.ll6 %v0 = call i32 asm sideeffect "; def $0", "=v"()
7 %v1 = call i32 asm sideeffect "; def $0", "=v"()
8 %v2 = call i32 asm sideeffect "; def $0", "=v"()
9 %v3 = call i32 asm sideeffect "; def $0", "=v"()
10 %v4 = call i32 asm sideeffect "; def $0", "=v"()
11 %v5 = call i32 asm sideeffect "; def $0", "=v"()
12 %v6 = call i32 asm sideeffect "; def $0", "=v"()
13 %v7 = call i32 asm sideeffect "; def $0", "=v"()
14 %v8 = call i32 asm sideeffect "; def $0", "=v"()
15 %v9 = call i32 asm sideeffect "; def $0", "=v"()
[all …]
H A Dattr-amdgpu-flat-work-group-size-vgpr-limit.ll15 %v0 = call i32 asm sideeffect "; def $0", "=v"()
16 %v1 = call i32 asm sideeffect "; def $0", "=v"()
17 %v2 = call i32 asm sideeffect "; def $0", "=v"()
18 %v3 = call i32 asm sideeffect "; def $0", "=v"()
19 %v4 = call i32 asm sideeffect "; def $0", "=v"()
20 %v5 = call i32 asm sideeffect "; def $0", "=v"()
21 %v6 = call i32 asm sideeffect "; def $0", "=v"()
22 %v7 = call i32 asm sideeffect "; def $0", "=v"()
23 %v8 = call i32 asm sideeffect "; def $0", "=v"()
24 %v9 = call i32 asm sideeffec
[all...]
H A Dexceed-max-sgprs.ll5 call void asm sideeffect "", "~{s[0:7]}" ()
6 call void asm sideeffect "", "~{s[8:15]}" ()
7 call void asm sideeffect "", "~{s[16:23]}" ()
8 call void asm sideeffect "", "~{s[24:31]}" ()
9 call void asm sideeffect "", "~{s[32:39]}" ()
10 call void asm sideeffect "", "~{s[40:47]}" ()
11 call void asm sideeffect "", "~{s[48:55]}" ()
12 call void asm sideeffect "", "~{s[56:63]}" ()
13 call void asm sideeffect "", "~{s[64:71]}" ()
14 call void asm sideeffect "", "~{s[72:79]}" ()
[all …]
H A Dsi-spill-sgpr-stack.ll
H A Dsgpr-spill-incorrect-fi-bookkeeping-bug.ll8 call void asm sideeffect "", "~{v[0:7]}" () #0
9 call void asm sideeffect "", "~{v[8:15]}" () #0
10 call void asm sideeffect "", "~{v[16:19]}"() #0
11 call void asm sideeffect "", "~{v[20:21]}"() #0
12 %val0 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
13 %val1 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
14 %val2 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
15 %val3 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
16 %val4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
17 %val5 = call <4 x i32> asm sideeffec
[all...]
H A Dinline-constraints.ll22 %v32 = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,v"(ptr addrspace(1) %ptr)
23 …%v2_32 = tail call <2 x i32> asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(ptr addrspace(1) %p…
24 %v64 = tail call i64 asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(ptr addrspace(1) %ptr)
25 …%v4_32 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(ptr addrspace(1) %p…
26 %v128 = tail call i128 asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(ptr addrspace(1) %ptr)
27 %s32 = tail call i32 asm sideeffect "s_load_dword $0, $1", "=s,s"(ptr addrspace(1) %ptr)
28 %s32_2 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(ptr addrspace(1) %ptr)
29 %s64 = tail call i64 asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(ptr addrspace(1) %ptr)
30 …%s4_32 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(ptr addrspace(1) %ptr)
31 %s128 = tail call i128 asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(ptr addrspace(1) %ptr)
[all …]
H A Dbranch-relax-spill.ll669 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
670 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
671 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
672 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
673 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
674 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
675 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
676 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
677 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
678 %sgpr9 = tail call i32 asm sideeffec
[all...]
H A Dmax-sgprs.ll6 call void asm sideeffect "", "~{s[0:7]}" ()
7 call void asm sideeffect "", "~{s[8:15]}" ()
8 call void asm sideeffect "", "~{s[16:23]}" ()
9 call void asm sideeffect "", "~{s[24:31]}" ()
10 call void asm sideeffect "", "~{s[32:39]}" ()
11 call void asm sideeffect "", "~{s[40:47]}" ()
12 call void asm sideeffect "", "~{s[48:55]}" ()
13 call void asm sideeffect "", "~{s[56:63]}" ()
14 call void asm sideeffect "", "~{s[64:71]}" ()
15 call void asm sideeffect "", "~{s[72:79]}" ()
[all …]
H A Dregalloc-illegal-eviction-assert.ll9 %asm.output = type { <16 x i32>, <8 x i32>, <5 x i32>, <4 x i32>, <16 x i32> }
16 ;%agpr0 = call i32 asm sideeffect "; def $0","=${a0}"()
17 %asm = call %asm.output asm sideeffect "; def $0 $1 $2 $3 $4","=v,=v,=v,=v,={a[0:15]}"()
18 %vgpr0 = extractvalue %asm.output %asm, 0
19 %vgpr1 = extractvalue %asm.output %asm, 1
20 %vgpr2 = extractvalue %asm
[all...]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A DPR3488.ll3 module asm "\09.section \22___kcrctab+numa_node\22, \22a\22\09"
4 module asm "\09.weak\09__crc_numa_node\09"
5 module asm "\09.long\09__crc_numa_node\09"
6 module asm "\09.previous\09\09\09\09\09"
7 module asm "\09.section \22___kcrctab+_numa_mem_\22, \22a\22\09"
8 module asm "\09.weak\09__crc__numa_mem_\09"
9 module asm "\09.long\09__crc__numa_mem_\09"
10 module asm "\09.previous\09\09\09\09\09"
11 module asm "\09.section \22___kcrctab+node_states\22, \22a\22\09"
12 module asm "\09.weak\09__crc_node_states\09"
[all …]
/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/
H A Dlong-branch-reg-all-sgpr-used.ll53 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #1
54 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #1
55 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #1
56 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #1
57 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #1
58 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #1
59 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #1
60 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #1
61 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #1
62 %sgpr9 = tail call i32 asm sideeffec
[all...]
/llvm-project/llvm/test/Analysis/UniformityAnalysis/AMDGPU/
H A Dinline-asm.ll8 %sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()
15 %sgpr = call i32 asm "s_mov_b32 s0, 0", "={s0}"()
20 ; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
22 %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
27 ; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()
29 %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()
34 ; CHECK: DIVERGENT: %vgpr = call i32 asm "; def $0", "=a"()
36 %vgpr = call i32 asm "; def $0", "=a"()
41 ; CHECK: DIVERGENT: %vgpr = call i32 asm "; def a0", "={a0}"()
43 %vgpr = call i32 asm "; def a0", "={a0}"()
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dbranch-relax-b.ll24 call void asm sideeffect ".space 2048", ""()
28 call void asm sideeffect ".space 8", ""()
64 %x0 = call i64 asm sideeffect "mov x0, 1", "={x0}"()
65 %x1 = call i64 asm sideeffect "mov x1, 1", "={x1}"()
66 %x2 = call i64 asm sideeffect "mov x2, 1", "={x2}"()
67 %x3 = call i64 asm sideeffect "mov x3, 1", "={x3}"()
68 %x4 = call i64 asm sideeffect "mov x4, 1", "={x4}"()
69 %x5 = call i64 asm sideeffect "mov x5, 1", "={x5}"()
70 %x6 = call i64 asm sideeffect "mov x6, 1", "={x6}"()
71 %x7 = call i64 asm sideeffect "mov x7, 1", "={x7}"()
[all …]
/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_syscall_linux_aarch64.inc16 register u64 x8 asm("x8") = nr;
17 register u64 x0 asm("x0");
18 asm volatile("svc 0"
28 register u64 x8 asm("x8") = nr;
29 register u64 x0 asm("x0") = arg1;
30 asm volatile("svc 0"
40 register u64 x8 asm("x8") = nr;
41 register u64 x0 asm("x0") = arg1;
42 register u64 x1 asm("x1") = arg2;
43 asm volatile("svc 0"
[all …]
H A Dsanitizer_syscall_linux_arm.inc16 register u32 r8 asm("r7") = nr;
17 register u32 r0 asm("r0");
18 asm volatile("swi #0"
28 register u32 r8 asm("r7") = nr;
29 register u32 r0 asm("r0") = arg1;
30 asm volatile("swi #0"
40 register u32 r8 asm("r7") = nr;
41 register u32 r0 asm("r0") = arg1;
42 register u32 r1 asm("r1") = arg2;
43 asm volatile("swi #0"
[all …]
H A Dsanitizer_syscall_linux_loongarch64.inc31 register u64 a7 asm("$a7") = nr;
32 register u64 a0 asm("$a0");
42 register u64 a7 asm("$a7") = nr;
43 register u64 a0 asm("$a0") = arg1;
53 register u64 a7 asm("$a7") = nr;
54 register u64 a0 asm("$a0") = arg1;
55 register u64 a1 asm("$a1") = arg2;
66 register u64 a7 asm("$a7") = nr;
67 register u64 a0 asm("$a0") = arg1;
68 register u64 a1 asm("$a1") = arg2;
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dcbz-implicit-it-range.ll14 tail call void asm sideeffect "movseq r0, #0\0A", ""()
15 tail call void asm sideeffect "movseq r0, #0\0A", ""()
16 tail call void asm sideeffect "movseq r0, #0\0A", ""()
17 tail call void asm sideeffect "movseq r0, #0\0A", ""()
18 tail call void asm sideeffect "movseq r0, #0\0A", ""()
19 tail call void asm sideeffect "movseq r0, #0\0A", ""()
20 tail call void asm sideeffect "movseq r0, #0\0A", ""()
21 tail call void asm sideeffect "movseq r0, #0\0A", ""()
22 tail call void asm sideeffect "movseq r0, #0\0A", ""()
23 tail call void asm sideeffect "movseq r0, #0\0A", ""()
[all …]
/llvm-project/llvm/test/CodeGen/X86/
H A Dpreserve_mostcc64-ret-double.ll13 %a0 = call i64 asm sideeffect "", "={rax}"() nounwind
14 %a1 = call i64 asm sideeffect "", "={rcx}"() nounwind
15 %a2 = call i64 asm sideeffect "", "={rdx}"() nounwind
16 %a3 = call i64 asm sideeffect "", "={r8}"() nounwind
17 %a4 = call i64 asm sideeffect "", "={r9}"() nounwind
18 %a5 = call i64 asm sideeffect "", "={r10}"() nounwind
19 %a6 = call i64 asm sideeffect "", "={r11}"() nounwind
20 %a10 = call <2 x double> asm sideeffect "", "={xmm0}"() nounwind
21 %a11 = call <2 x double> asm sideeffect "", "={xmm1}"() nounwind
22 %a12 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
[all …]
H A D2010-09-16-asmcrash.ll4 module asm ".weak sem_close"
5 module asm ".equ sem_close, _sem_close"
6 module asm ".weak sem_destroy"
7 module asm ".equ sem_destroy, _sem_destroy"
8 module asm ".weak sem_getvalue"
9 module asm ".equ sem_getvalue, _sem_getvalue"
10 module asm ".weak sem_init"
11 module asm ".equ sem_init, _sem_init"
12 module asm ".weak sem_open"
13 module asm ".equ sem_open, _sem_open"
[all …]
/llvm-project/llvm/test/CodeGen/MSP430/
H A Dinline-asm-register-names.ll5 ; Test that correct register names are accepted *inside* inline asm listings.
10 call void asm sideeffect "push r0", ""() nounwind
12 call void asm sideeffect "push r1", ""() nounwind
14 call void asm sideeffect "push r2", ""() nounwind
16 call void asm sideeffect "push r3", ""() nounwind
18 call void asm sideeffect "push r4", ""() nounwind
20 call void asm sideeffect "push r5", ""() nounwind
22 call void asm sideeffect "push r6", ""() nounwind
24 call void asm sideeffect "push r7", ""() nounwind
26 call void asm sideeffect "push r8", ""() nounwind
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Danyregcc-vec.ll40 …call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~…
61 %a0 = call <2 x i64> asm sideeffect "", "={v0}"() nounwind
62 %a1 = call <2 x i64> asm sideeffect "", "={v1}"() nounwind
63 %a2 = call <2 x i64> asm sideeffect "", "={v2}"() nounwind
64 %a3 = call <2 x i64> asm sideeffect "", "={v3}"() nounwind
65 %a4 = call <2 x i64> asm sideeffect "", "={v4}"() nounwind
66 %a5 = call <2 x i64> asm sideeffect "", "={v5}"() nounwind
67 %a6 = call <2 x i64> asm sideeffect "", "={v6}"() nounwind
68 %a7 = call <2 x i64> asm sideeffect "", "={v7}"() nounwind
69 %a8 = call <2 x i64> asm sideeffect "", "={v8}"() nounwind
[all …]

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