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Searched refs:CondCode (Results 1 – 25 of 143) sorted by relevance

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/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64GlobalISelUtils.cpp127 const CmpInst::Predicate P, AArch64CC::CondCode &CondCode,
128 AArch64CC::CondCode &CondCode2) { in changeFCMPPredToAArch64CC()
134 CondCode = AArch64CC::EQ; in changeFCMPPredToAArch64CC()
137 CondCode = AArch64CC::GT; in changeFCMPPredToAArch64CC()
140 CondCode = AArch64CC::GE; in changeFCMPPredToAArch64CC()
143 CondCode = AArch64CC::MI; in changeFCMPPredToAArch64CC()
146 CondCode = AArch64CC::LS; in changeFCMPPredToAArch64CC()
149 CondCode = AArch64CC::MI; in changeFCMPPredToAArch64CC()
153 CondCode in changeFCMPPredToAArch64CC()
129 changeFCMPPredToAArch64CC(const CmpInst::Predicate P,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2) changeFCMPPredToAArch64CC() argument
189 changeVectorFCMPPredToAArch64CC(const CmpInst::Predicate P,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2,bool & Invert) changeVectorFCMPPredToAArch64CC() argument
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H A DAArch64GlobalISelUtils.h69 AArch64CC::CondCode &CondCode,
70 AArch64CC::CondCode &CondCode2);
80 AArch64CC::CondCode &CondCode,
81 AArch64CC::CondCode &CondCode2,
/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1597 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
1610 enum CondCode {
1643 inline bool isSignedIntSetCC(CondCode Code) {
1649 inline bool isUnsignedIntSetCC(CondCode Code) {
1655 inline bool isIntEqualitySetCC(CondCode Code) {
1661 inline bool isFPEqualitySetCC(CondCode Code) {
1668 inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; }
1673 inline unsigned getUnorderedFlavor(CondCode Cond) {
1679 CondCode getSetCCInverse(CondCode Operatio
1554 enum CondCode { global() enum
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H A DAnalysis.h109 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
113 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
117 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
121 ICmpInst::Predicate getICmpCondCode(ISD::CondCode Pred);
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp102 using CmpInfo = std::tuple<int, unsigned, AArch64CC::CondCode>;
112 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
114 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
230 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) { in getAdjustedCmp()
244 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { in adjustCmp()
275 AArch64CC::CondCode Cmp; in modifyCmp()
304 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
308 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
318 AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm) in adjustTo()
375 AArch64CC::CondCode HeadCmp; in runOnMachineFunction()
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H A DAArch64SpeculationHardening.cpp151 AArch64CC::CondCode &CondCode) const;
153 AArch64CC::CondCode &CondCode, DebugLoc DL) const;
185 AArch64CC::CondCode &CondCode) const {
208 // translate analyzeBranchCondCode to CondCode. in endsWithCondControlFlow()
210 CondCode = AArch64CC::CondCode(analyzeBranchCondCode[0].getImm()); in endsWithCondControlFlow()
223 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode in insertFullSpeculationBarrier()
226 insertTrackingCode(MachineBasicBlock & SplitEdgeBB,AArch64CC::CondCode & CondCode,DebugLoc DL) const insertTrackingCode() argument
247 AArch64CC::CondCode CondCode; instrumentControlFlow() local
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/llvm-project/llvm/lib/Target/VE/
H A DVE.h42 enum CondCode { enum
85 inline static const char *VECondCodeToString(VECC::CondCode CC) { in VECondCodeToString()
114 inline static VECC::CondCode stringToVEICondCode(StringRef S) { in stringToVEICondCode()
115 return StringSwitch<VECC::CondCode>(S) in stringToVEICondCode()
128 inline static VECC::CondCode stringToVEFCondCode(StringRef S) { in stringToVEFCondCode()
129 return StringSwitch<VECC::CondCode>(S) in stringToVEFCondCode()
150 inline static bool isIntVECondCode(VECC::CondCode CC) { in isIntVECondCode()
154 inline static unsigned VECondCodeToVal(VECC::CondCode CC) { in VECondCodeToVal()
205 inline static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger) { in VEValToCondCode()
H A DVEISelLowering.h69 inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) { in intCondCode2Icc()
97 inline static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC) { in fpCondCode2Fcc()
/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp33 enum CondCode {
129 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in IsBR_JT()
142 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondFromBranchOpc()
153 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetCondBranchFromCond()
208 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in analyzeBranch()
229 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in analyzeBranch()
285 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
402 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Con in reverseBranchCondition()
37 enum CondCode { global() enum
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/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCondCode.h10 enum CondCode { enum
34 inline static StringRef lanaiCondCodeToString(LPCC::CondCode CC) { in lanaiCondCodeToString()
73 inline static CondCode suffixToLanaiCondCode(StringRef S) { in suffixToLanaiCondCode()
74 return StringSwitch<CondCode>(S) in suffixToLanaiCondCode()
H A DLanaiInstrInfo.cpp124 static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) { in getOppositeCondition()
353 SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4> in optimizeCompareInstr()
373 LPCC::CondCode CC; in optimizeCompareInstr()
374 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
377 LPCC::CondCode NewCC = getOppositeCondition(CC); in optimizeCompareInstr()
521 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
523 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode))); in optimizeSelect()
525 NewMI.addImm(CondCode); in optimizeSelect()
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/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h48 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
60 CondCode getCondFromMI(const MachineInstr &MI);
63 CondCode getCondFromBranch(const MachineInstr &MI);
66 CondCode getCondFromSETCC(const MachineInstr &MI);
69 CondCode getCondFromCMov(const MachineInstr &MI);
72 CondCode getCondFromCFCMov(const MachineInstr &MI);
75 CondCode getCondFromCCMP(const MachineInstr &MI);
78 int getCCMPCondFlagsFromCondCode(CondCode CC);
88 CondCode GetOppositeBranchCondition(CondCode C
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H A DX86FlagsCopyLowering.cpp98 const DebugLoc &TestLoc, X86::CondCode Cond);
101 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
719 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs()
737 const DebugLoc &TestLoc, X86::CondCode Cond) {
749 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) {
776 X86::CondCode Cond = X86::getCondFromSETCC(MI); in rewriteSetCC()
814 X86::CondCode Cond = X86::COND_B; // CF == 1 in rewriteArithmetic()
841 static X86::CondCode getImplicitCondFromMI(unsigned Opc) { in rewriteArithmetic()
863 static unsigned getOpcodeWithCC(unsigned Opc, X86::CondCode CC) { in getImplicitCondFromMI()
891 X86::CondCode C in rewriteMI()
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H A DX86CmovConversion.cpp297 X86::CondCode FirstCC = X86::COND_INVALID, FirstOppCC = X86::COND_INVALID, in collectCmovCandidates()
309 X86::CondCode CC = X86::getCondFromCMov(I); in collectCmovCandidates()
672 X86::CondCode CC = X86::CondCode(X86::getCondFromCMov(MI)); in convertCmovInstsToBranches()
673 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC); in convertCmovInstsToBranches()
/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp331 unsigned CondCode; in parseJccInstruction()
333 CondCode = MSP430CC::COND_NE; in parseJccInstruction()
335 CondCode = MSP430CC::COND_E; in parseJccInstruction()
337 CondCode = MSP430CC::COND_LO; in parseJccInstruction()
339 CondCode = MSP430CC::COND_HS; in parseJccInstruction()
341 CondCode = MSP430CC::COND_N; in parseJccInstruction()
343 CondCode = MSP430CC::COND_GE; in parseJccInstruction()
345 CondCode = MSP430CC::COND_L; in parseJccInstruction()
347 CondCode = MSP430CC::COND_NONE; in parseJccInstruction()
351 if (CondCode in parseJccInstruction()
334 unsigned CondCode; parseJccInstruction() local
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/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.h34 enum CondCode { enum
58 static inline M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC) { in GetOppositeBranchCondition()
97 static inline unsigned GetCondBranchFromCond(M68k::CondCode CC) { in GetCondBranchFromCond()
132 static inline M68k::CondCode GetCondFromBranchOpc(unsigned Opcode) { in GetCondFromBranchOpc()
H A DM68kISelLowering.cpp1653 static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, in getBitTestCondition()
1669 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition()
1675 static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, in LowerAndToBTST()
1723 static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode) { in TranslateIntegerM68kCC()
1750 /// Do a one-to-one translation of a ISD::CondCode to the M68k-specific
1753 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, in TranslateM68kCC()
1834 static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, in LowerTruncateToBTST()
2132 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC, in LowerToBTST()
2149 ISD::CondCode C in LowerSETCC()
2282 unsigned CondCode = Cond.getConstantOperandVal(0); LowerSELECT() local
2379 unsigned CondCode = CC->getAsZExtVal(); LowerSELECT() local
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/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h37 enum CondCode { enum
47 CondCode getOppositeBranchCondition(CondCode);
48 unsigned getBrCond(CondCode CC, bool Imm = false);
68 const MCInstrDesc &getBrCond(RISCVCC::CondCode CC, bool Imm = false) const;
H A DRISCVISelDAGToDAG.h94 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
168 // condition code. The CondCode must be one of those supported by the RISC-V
170 static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) { in getRISCVCCForIntCC()
173 llvm_unreachable("Unsupported CondCode"); in getRISCVCCForIntCC()
/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInstPrinter.cpp54 static const char *ARCCondCodeToString(ARCCC::CondCode CC) { in ARCCondCodeToString()
172 O << ARCCondCodeToString((ARCCC::CondCode)Op.getImm()); in printPredicateOperand()
184 O << ARCCondCodeToString((ARCCC::CondCode)MI->getOperand(OpNum).getImm()); in printCCOperand()
/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp287 LPCC::CondCode CC =
288 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm()); in printCCOperand()
298 LPCC::CondCode CC =
299 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm()); in printPredicateOperand()
/llvm-project/llvm/test/TableGen/
H A DGlobalISelEmitter-setcc.td
/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.h32 enum CondCode { enum
72 const char *MipsFCCToString(Mips::CondCode CC);
/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h254 enum CondCode { // Meaning (integer) Meaning (floating-point)
281 inline static const char *getCondCodeName(CondCode Code) {
303 inline static CondCode getInvertedCondCode(CondCode Code) {
306 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); in getInvertedCondCode()
312 inline static CondCode getSwappedCondition(CondCode CC) {
343 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { in SysAlias()
255 enum CondCode { // Meaning (integer) Meaning (floating-point) global() enum
/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp1056 LPCC::CondCode CondCode = in splitMnemonic()
1058 if (CondCode != LPCC::UNKNOWN) { in splitMnemonic() local
1062 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc)); in splitMnemonic()
1076 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); in splitMnemonic()
1077 if (CondCode != LPCC::UNKNOWN) { in splitMnemonic()
1091 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc)); in splitMnemonic()
1078 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); splitMnemonic() local

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