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/llvm-project/bolt/include/bolt/Passes/
H A DLivenessAnalysis.h25 class LivenessAnalysis : public DataflowAnalysis<LivenessAnalysis, BitVector,
28 DataflowAnalysis<LivenessAnalysis, BitVector, true, RegStatePrinter>;
29 friend class DataflowAnalysis<LivenessAnalysis, BitVector, true,
40 BitVector BV = (*this->getStateAt(PP)); in isAlive()
41 const BitVector &RegAliases = BC.MIB->getAliases(Reg); in isAlive()
51 BitVector BV = *this->getStateAt(P); in scavengeRegAfter()
53 BitVector GPRegs(NumRegs, false); in scavengeRegAfter()
57 BitVector FP = BC.MIB->getAliases(BC.MIB->getFramePointer()); in scavengeRegAfter()
72 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
76 BitVector State(NumRegs, false); in getStartingStateAtBB()
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H A DReachingDefOrUse.h31 friend class DataflowAnalysis<ReachingDefOrUse<Def>, BitVector, !Def>;
43 BitVector BV = BitVector(this->BC.MRI->getNumRegs(), false); in isReachedBy()
79 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
80 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
83 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
84 return BitVector(this->NumInstrs, false); in getStartingStateAtPoint()
87 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
95 BitVector XClobbers = BitVector(this->BC.MRI->getNumRegs(), false); in doesXKillsY()
96 BitVector YClobbers = BitVector(this->BC.MRI->getNumRegs(), false); in doesXKillsY()
115 BitVector computeNext(const MCInst &Point, const BitVector &Cur) { in computeNext()
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H A DStackAllocationAnalysis.h28 friend class DataflowAnalysis<StackAllocationAnalysis, BitVector>;
44 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB);
46 BitVector getStartingStateAtPoint(const MCInst &Point);
48 void doConfluence(BitVector &StateOut, const BitVector &StateIn);
50 BitVector doKill(const MCInst &Point, const BitVector &StateIn,
53 void doConfluenceWithLP(BitVector &StateOut, const BitVector &StateIn,
56 BitVector computeNext(const MCInst &Point, const BitVector &Cur);
H A DStackReachingUses.h27 friend class DataflowAnalysis<StackReachingUses, BitVector, true>;
57 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
58 return BitVector(NumInstrs, false); in getStartingStateAtBB()
61 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
62 return BitVector(NumInstrs, false); in getStartingStateAtPoint()
65 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
72 BitVector computeNext(const MCInst &Point, const BitVector &Cur);
H A DReachingInsns.h25 friend class DataflowAnalysis<ReachingInsns<Backward>, BitVector, Backward>;
61 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
62 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
65 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
66 return BitVector(this->NumInstrs, false); in getStartingStateAtPoint()
69 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
73 BitVector computeNext(const MCInst &Point, const BitVector &Cur) { in computeNext()
74 BitVector Next = Cur; in computeNext()
H A DDominatorAnalysis.h30 friend class DataflowAnalysis<DominatorAnalysis<Backward>, BitVector,
117 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB) { in getStartingStateAtBB()
121 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
123 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
124 return BitVector(this->NumInstrs, true); in getStartingStateAtBB()
127 BitVector getStartingStateAtPoint(const MCInst &Point) { in getStartingStateAtPoint()
128 return BitVector(this->NumInstrs, true); in getStartingStateAtPoint()
131 void doConfluence(BitVector &StateOut, const BitVector &StateIn) { in doConfluence()
135 BitVector computeNext(const MCInst &Point, const BitVector &Cur) { in computeNext()
136 BitVector Next = Cur; in computeNext()
H A DRegAnalysis.h31 BitVector getFunctionUsedRegsList(const BinaryFunction *Func);
37 BitVector getFunctionClobberList(const BinaryFunction *Func);
45 void getInstUsedRegsList(const MCInst &Inst, BitVector &RegSet,
51 void getInstClobberList(const MCInst &Inst, BitVector &KillSet) const;
55 bool isConservative(BitVector &Vec) const;
69 std::map<const BinaryFunction *, BitVector> RegsKilledMap;
72 std::map<const BinaryFunction *, BitVector> RegsGenMap;
83 void beConservative(BitVector &Result) const;
H A DStackAvailableExpressions.h27 friend class DataflowAnalysis<StackAvailableExpressions, BitVector>;
41 BitVector getStartingStateAtBB(const BinaryBasicBlock &BB);
42 BitVector getStartingStateAtPoint(const MCInst &Point);
43 void doConfluence(BitVector &StateOut, const BitVector &StateIn);
47 BitVector computeNext(const MCInst &Point, const BitVector &Cur);
H A DRegReAssign.h22 BitVector ClassicRegs;
23 BitVector CalleeSaved;
24 BitVector ClassicCSR;
25 BitVector ExtendedCSR;
26 BitVector GPRegs;
/llvm-project/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.h20 #include "llvm/ADT/BitVector.h"
28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
29 const BitVector &SourceBits);
44 const BitVector &ReservedReg,
51 const BitVector &sourceBits() const { return SourceBits; } in sourceBits()
53 // Retrieves all the touched registers as a BitVector.
54 const BitVector &aliasedBits() const { return AliasedBits; } in aliasedBits()
68 const BitVector &OriginalBits);
70 BitVector SourceBits;
71 BitVector AliasedBit
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H A DMCInstrDescView.h92 /// A cache of BitVector to reuse between Instructions.
96 // Finds or allocates the provided BitVector in the cache and retrieves it's
98 const BitVector *getUnique(BitVector &&BV) const;
101 mutable std::vector<std::unique_ptr<BitVector>> Cache;
134 bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
140 bool hasAliasingNotMemoryRegisters(const BitVector &ForbiddenRegisters) const;
144 const BitVector &ForbiddenRegisters) const;
165 const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
166 const BitVector
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H A DParallelSnippetGenerator.cpp147 const LLVMState &State, const BitVector &ForbiddenRegisters, in generateSingleRegisterForInstrAvoidingDefUseOverlap()
148 const BitVector &ImplicitUseAliases, const BitVector &ImplicitDefAliases, in generateSingleRegisterForInstrAvoidingDefUseOverlap()
149 const BitVector &Uses, const BitVector &Defs, const InstructionTemplate &IT, in generateSingleRegisterForInstrAvoidingDefUseOverlap()
168 BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
169 const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
178 BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
183 const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
191 const BitVector UseAliase in generateSingleRegisterForInstrAvoidingDefUseOverlap()
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H A DSnippetGenerator.h39 const BitVector &ForbiddenRegisters);
67 const BitVector &ExtraForbiddenRegs) const;
81 const BitVector &ForbiddenRegisters) const = 0;
94 size_t randomBit(const BitVector &Vector);
97 std::optional<int> getFirstCommonBit(const BitVector &A, const BitVector &B);
107 const BitVector &ForbiddenRegs,
H A DMCInstrDescView.cpp82 const BitVector *BitVectorCache::getUnique(BitVector &&BV) const { in getUnique()
86 Cache.push_back(std::make_unique<BitVector>()); in getUnique()
95 const BitVector *ImplDefRegs, in Instruction()
96 const BitVector *ImplUseRegs, in Instruction()
97 const BitVector *AllDefRegs, in Instruction()
98 const BitVector *AllUseRegs, in Instruction()
99 const BitVector *NonMemoryRegs) in Instruction()
166 BitVector ImplDefRegs = RATC.emptyRegisters(); in create()
167 BitVector ImplUseReg in create()
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H A DRegisterAliasing.cpp14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, in getAliasedBits()
15 const BitVector &SourceBits) { in getAliasedBits()
16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits()
32 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg, in RegisterAliasingTracker()
49 const MCRegisterInfo &RegInfo, const BitVector &SourceBits) { in FillOriginAndAliasedBits()
61 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg) in RegisterAliasingTrackerCache()
82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString()
H A DSnippetGenerator.cpp43 const BitVector &ExtraForbiddenRegs) const { in generateConfigurations()
44 BitVector ForbiddenRegs = State.getRATC().reservedRegisters(); in generateConfigurations()
113 BitVector DefinedRegs = State.getRATC().emptyRegisters(); in computeRegisterInitialValues()
157 const BitVector &ForbiddenRegisters) { in generateSelfAliasingCodeTemplates()
223 size_t randomBit(const BitVector &Vector) { in getFirstCommonBit()
231 std::optional<int> getFirstCommonBit(const BitVector &A, const BitVector &B) { in setRandomAliasing()
232 BitVector Intersect = A; in setRandomAliasing()
252 const BitVector &ForbiddenRegs) { in randomizeMCOperand()
286 const BitVector in randomizeUnsetVariables()
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/llvm-project/bolt/lib/Passes/
H A DStackAvailableExpressions.cpp48 BitVector
53 return BitVector(NumInstrs, false); in getStartingStateAtBB()
54 return BitVector(NumInstrs, true); in getStartingStateAtBB()
57 BitVector
59 return BitVector(NumInstrs, true); in getStartingStateAtPoint()
62 void StackAvailableExpressions::doConfluence(BitVector &StateOut, in doConfluence()
63 const BitVector &StateIn) { in doConfluence()
95 BitVector XClobbers = BitVector(BC.MRI->getNumRegs(), false); in doesXKillsY()
96 BitVector YClobbers = BitVector(BC.MRI->getNumRegs(), false); in doesXKillsY()
110 BitVector StackAvailableExpressions::computeNext(const MCInst &Point, in computeNext()
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H A DRegAnalysis.cpp46 BitVector RegsKilled = getFunctionClobberList(Func); in RegAnalysis()
55 BitVector RegsGen = getFunctionUsedRegsList(Func); in RegAnalysis()
91 const BitVector &RegsKilled = Iter->second; in RegAnalysis()
98 const BitVector &RegsUsed = RegsGenMap.find(Func)->second; in RegAnalysis()
109 void RegAnalysis::beConservative(BitVector &Result) const { in beConservative()
115 BitVector BV(BC.MRI->getNumRegs(), false); in beConservative()
127 bool RegAnalysis::isConservative(BitVector &Vec) const { in isConservative()
132 BitVector BV(BC.MRI->getNumRegs(), false); in isConservative()
143 void RegAnalysis::getInstUsedRegsList(const MCInst &Inst, BitVector &RegSet, in getInstUsedRegsList()
192 BitVector &KillSet) const { in getInstClobberList()
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H A DStackAllocationAnalysis.cpp42 BitVector
44 return BitVector(this->NumInstrs, false); in getStartingStateAtBB()
47 BitVector
49 return BitVector(this->NumInstrs, false); in getStartingStateAtPoint()
52 void StackAllocationAnalysis::doConfluence(BitVector &StateOut, in doConfluence()
53 const BitVector &StateIn) { in doConfluence()
57 BitVector StackAllocationAnalysis::doKill(const MCInst &Point, in doKill()
58 const BitVector &StateIn, in doKill()
61 BitVector Next = StateIn; in doKill()
85 void StackAllocationAnalysis::doConfluenceWithLP(BitVector &StateOut, in doConfluenceWithLP()
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H A DDataflowAnalysis.cpp20 raw_ostream &operator<<(raw_ostream &OS, const BitVector &State) { in operator <<()
26 BitVector BV = State; in operator <<()
77 void RegStatePrinter::print(raw_ostream &OS, const BitVector &State) const { in print()
84 BitVector BV = State; in print()
/llvm-project/llvm/include/llvm/ADT/
H A DBitVector.h82 class BitVector {
105 reference(BitVector &b, unsigned Idx) { in reference()
131 typedef const_set_bits_iterator_impl<BitVector> const_set_bits_iterator;
145 BitVector() = default;
149 explicit BitVector(unsigned s, bool t = false)
351 BitVector &set() { in set()
357 BitVector &set(unsigned Idx) { in set()
364 BitVector &set(unsigned I, unsigned E) { in set()
392 BitVector &reset() { in reset()
397 BitVector &reset(unsigned Idx) { in reset()
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/llvm-project/mlir/lib/Transforms/
H A DRemoveDeadValues.cpp81 BitVector nonLiveArgs; in hasLive()
82 BitVector nonLiveRets; in hasLive()
87 BitVector nonLive; in hasLive()
92 BitVector nonLiveArgs;
98 BitVector nonLiveOperands; in markLives()
128 /// Return a BitVector of size `values.size()` where its i-th bit is 1 iff the in dropUsesAndEraseResults()
130 static BitVector markLives(ValueRange values, const DenseSet<Value> &nonLiveSet, in dropUsesAndEraseResults()
132 BitVector lives(values.size(), true); in dropUsesAndEraseResults()
158 const BitVector &nonLive) {
168 static void dropUsesAndEraseResults(Operation *op, BitVector toEras
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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp25 #include "llvm/ADT/BitVector.h"
99 BitVector Defs, Uses;
102 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
126 void getSubRegs(unsigned Reg, BitVector &SRs) const;
127 void expandReg(unsigned Reg, BitVector &Set) const;
128 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
129 BitVector &Uses) const;
145 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {
150 void HexagonGenMux::expandReg(unsigned Reg, BitVector in getSubRegs()
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/llvm-project/llvm/include/llvm/Analysis/
H A DStackLifetime.h46 BitVector Begin;
49 BitVector End;
52 BitVector LiveIn;
55 BitVector LiveOut;
64 BitVector Bits;
113 BitVector InterestingAllocas;
169 static inline raw_ostream &operator<<(raw_ostream &OS, const BitVector &V) {
/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h63 BitVector Seen;
76 using EntryInfoMap = DenseMap<LiveRange *, std::pair<BitVector, BitVector>>;
130 MachineBasicBlock &MBB, BitVector &DefOnEntry,
131 BitVector &UndefOnEntry);

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