Lines Matching refs:BitVector

147     const LLVMState &State, const BitVector &ForbiddenRegisters,
148     const BitVector &ImplicitUseAliases, const BitVector &ImplicitDefAliases,
149     const BitVector &Uses, const BitVector &Defs, const InstructionTemplate &IT,
168       BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits();
169       const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses);
178   BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits();
183     const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses);
191       const BitVector UseAliases = getAliasedBits(State.getRegInfo(), Uses);
203     const BitVector DefsAliases = getAliasedBits(State.getRegInfo(), Defs);
215     const LLVMState &State, const BitVector &ForbiddenRegisters,
216     const BitVector &ImplicitUseAliases, const BitVector &ImplicitDefAliases,
217     BitVector &Uses, BitVector &Defs, InstructionTemplate IT,
254     RegRandomizationStrategy S, const BitVector &ForbiddenRegisters) {
258   BitVector ImplicitUses(State.getRegInfo().getNumRegs());
259   BitVector ImplicitDefs(State.getRegInfo().getNumRegs());
271   const BitVector ImplicitUseAliases =
273   const BitVector ImplicitDefAliases =
276   BitVector Defs(State.getRegInfo().getNumRegs());
277   BitVector Uses(State.getRegInfo().getNumRegs());
296     InstructionTemplate Variant, const BitVector &ForbiddenRegisters) const {