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Searched refs:AlignedAddr (Results 1 – 15 of 15) sorted by relevance

/llvm-project/clang/test/CodeGen/
H A Darm-vector-align.c13 typedef float AlignedAddr __attribute__ ((aligned (16))); typedef
14 void t1(AlignedAddr *addr1, AlignedAddr *addr2) { in t1()
/llvm-project/llvm/include/llvm/Support/
H A DAllocator.h193 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in AllocateSlow()
194 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in AllocateSlow()
195 char *AlignedPtr = (char*)AlignedAddr; in AllocateSlow()
203 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in AllocateSlow()
204 assert(AlignedAddr + SizeToAllocate <= (uintptr_t)End && in AllocateSlow()
206 char *AlignedPtr = (char*)AlignedAddr; in AllocateSlow()
191 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); AllocateSlow() local
201 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); AllocateSlow() local
/llvm-project/clang/test/Analysis/inlining/
H A Dplacement-new-fp-suppression.cpp57 uintptr_t AlignedAddr = alignAddr(Allocator.Allocate(PaddedSize, 0), in Allocate() local
59 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
/llvm-project/llvm/lib/CodeGen/
H A DAtomicExpandPass.cpp746 Value *AlignedAddr = nullptr; in createMaskInstrs()
768 O << " AlignedAddr: "; in createMaskInstrs()
769 PrintObj(PMV.AlignedAddr); in createMaskInstrs()
789 /// AlignedAddr: Addr rounded down to a multiple of WordSize in createMaskInstrs()
818 PMV.AlignedAddr = Addr; in insertMaskedValue()
834 PMV.AlignedAddr = Builder.CreateIntrinsic(
837 "AlignedAddr"); in performMaskedAtomicOp()
843 PMV.AlignedAddr = Addr; in performMaskedAtomicOp()
991 Builder, PMV.WordType, PMV.AlignedAddr, PMV.AlignedAddrAlignment, in widenPartwordAtomicRMW()
995 OldResult = insertRMWLLSCLoop(Builder, PMV.WordType, PMV.AlignedAddr, in widenPartwordAtomicRMW()
684 Value *AlignedAddr = nullptr; global() member
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/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dmmra.ll73 ; CHECK-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, mmra !2 :: (load (s32) from %ir.AlignedAddr)
87 ; CHECK-NEXT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY4]], killed [[COPY6]], 0, 1, implicit $exec, implicit $flat_scr, mmra !2 :: (load store release monotonic (s32) on %ir.AlignedAddr)
129 ; CHECK-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, mmra !1 :: (load (s32) from %ir.AlignedAddr)
145 ; CHECK-NEXT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY4]], killed [[COPY6]], 0, 1, implicit $exec, implicit $flat_scr, mmra !1 :: (load store acquire acquire (s32) on %ir.AlignedAddr)
253 ; CHECK-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY31]], 0, 0, implicit $exec, implicit $flat_scr, mmra !0 :: (load (s32) from %ir.AlignedAddr)
267 ; CHECK-NEXT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY30]], killed [[COPY32]], 0, 1, implicit $exec, implicit $flat_scr, mmra !0 :: (load store release monotonic (s32) on %ir.AlignedAddr)
/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h201 Value *AlignedAddr, Value *Incr,
211 Value *AlignedAddr, Value *CmpVal, in getExtendForAtomicOps()
H A DLoongArchISelLowering.cpp5916 Value *AlignedAddr = Builder.CreateIntrinsic(
5919 "AlignedAddr");
5940 Builder.CreateAtomicRMW(Op, AlignedAddr, NewOperand, Align(MinWordSize),
6045 IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
6056 Type *Tys[] = {AlignedAddr->getType()};
6058 CmpXchgIntrID, Tys, {AlignedAddr, CmpVal, NewVal, Mask, FailureOrdering});
6064 IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
6074 return Builder.CreateAtomicRMW(AtomicRMWInst::And, AlignedAddr,
6078 return Builder.CreateAtomicRMW(AtomicRMWInst::Or, AlignedAddr, Mask,
6085 Type *Tys[] = {AlignedAddr
4635 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
4656 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) const emitMaskedAtomicRMWIntrinsic() argument
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/llvm-project/compiler-rt/lib/sanitizer_common/tests/
H A Dsanitizer_allocator_test.cpp297 AlignedAddr = RoundUpTo(reinterpret_cast<uptr>(BasePtr), kAllocatorSize); in ScopedPremappedHeap()
302 uptr Addr() { return AlignedAddr; }
306 uptr AlignedAddr;
305 uptr AlignedAddr; global() member in ScopedPremappedHeap
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h792 Value *AlignedAddr, Value *Incr,
799 Value *AlignedAddr, Value *CmpVal, in computeVLMAX()
H A DRISCVISelLowering.cpp21614 IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
21624 return Builder.CreateAtomicRMW(AtomicRMWInst::And, AlignedAddr,
21628 return Builder.CreateAtomicRMW(AtomicRMWInst::Or, AlignedAddr, Mask,
21635 Type *Tys[] = {AlignedAddr->getType()}; in lowerInterleavedLoad()
21661 {AlignedAddr, Incr, Mask, SextShamt, Ordering});
21664 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
21687 IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in lowerInterleavedStore()
21698 Type *Tys[] = {AlignedAddr->getType()}; in lowerInterleavedStore()
21700 CmpXchgIntrID, Tys, {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); in lowerInterleavedStore()
20972 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) const emitMaskedAtomicRMWIntrinsic() argument
21045 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h938 AtomicRMWInst *AI, Value *AlignedAddr,
944 Value *AlignedAddr, Value *CmpVal,
H A DPPCISelLowering.cpp19157 IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
19169 {AlignedAddr, IncrLo, IncrHi});
19179 IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
19196 Builder.CreateCall(IntCmpXchg, {AlignedAddr, CmpLo, CmpHi, NewLo, NewHi});
18816 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) const emitMaskedAtomicRMWIntrinsic() argument
18838 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1738 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword()
1857 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1884 .addReg(AlignedAddr) in emitAtomicCmpSwap()
1987 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicCmpSwapPartword()
2044 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
2076 .addReg(AlignedAddr) in lowerBRCOND()
1702 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); emitAtomicBinaryPartword() local
1951 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); emitAtomicCmpSwapPartword() local
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4931 SDValue &AlignedAddr, SDValue &BitShift,
4937 AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
4981 SDValue AlignedAddr, BitShift, NegBitShift;
4982 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift);
4999 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in chooseShuffleOpNos()
5077 SDValue AlignedAddr, BitShift, NegBitShift; in matchDoublePermute()
5078 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift); in matchDoublePermute()
5082 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
4564 getCSAddressAndShifts(SDValue Addr,SelectionDAG & DAG,SDLoc DL,SDValue & AlignedAddr,SDValue & BitShift,SDValue & NegBitShift) getCSAddressAndShifts() argument
4613 SDValue AlignedAddr, BitShift, NegBitShift; lowerATOMIC_LOAD_OP() local
4709 SDValue AlignedAddr, BitShift, NegBitShift; lowerATOMIC_CMP_SWAP() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2204 Value *AlignedAddr, Value *Incr,
2244 IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
2182 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) emitMaskedAtomicRMWIntrinsic() argument
2217 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) emitMaskedAtomicCmpXchgIntrinsic() argument