| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 79 const TargetRegisterClass *RC) const;
106 const TargetRegisterClass *
107 getLargestLegalSuperClass(const TargetRegisterClass *RC,
139 const TargetRegisterClass *getPointerRegClass(
146 const TargetRegisterClass *
147 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
185 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
188 const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth) const;
191 const TargetRegisterClass *
195 static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
[all …]
|
| H A D | GCNRewritePartialRegUses.cpp | 81 const TargetRegisterClass *RC;
87 SubRegInfo(const TargetRegisterClass *RC_ = nullptr) : RC(RC_) {} in SubRegInfo()
97 const TargetRegisterClass *getMinSizeReg(const TargetRegisterClass *RC,
115 const TargetRegisterClass *
116 getRegClassWithShiftedSubregs(const TargetRegisterClass *RC, unsigned RShift,
128 const TargetRegisterClass *getOperandRegClass(MachineOperand &MO) const;
143 const uint32_t *getSuperRegClassMask(const TargetRegisterClass *RC,
147 mutable SmallDenseMap<std::pair<const TargetRegisterClass *, unsigned>,
187 GCNRewritePartialRegUses::getSuperRegClassMask(const TargetRegisterClass *R
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 45 class TargetRegisterClass {
49 using sc_iterator = const TargetRegisterClass* const *;
124 /// Return true if the specified TargetRegisterClass in hasSubClass()
125 /// is a proper sub-class of this TargetRegisterClass. in hasSubClass()
126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
136 /// Return true if the specified TargetRegisterClass is a in hasSuperClass()
137 /// proper super-class of this TargetRegisterClass. in hasSuperClass()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *R in hasSuperClassEq()
[all...] |
| H A D | RegisterClassInfo.h | 75 void compute(const TargetRegisterClass *RC) const;
78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
131 uint8_t getMinCost(const TargetRegisterClass *RC) const {
139 unsigned getLastCostChange(const TargetRegisterClass *RC) const {
|
| H A D | LiveStacks.h | 32 class TargetRegisterClass; variable
47 std::map<int, const TargetRegisterClass *> S2RCMap;
66 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
84 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass()
86 std::map<int, const TargetRegisterClass *>::const_iterator I = in getIntervalRegClass()
|
| H A D | RegisterScavenging.h | 31 class TargetRegisterClass; variable
105 BitVector getRegsAvailable(const TargetRegisterClass *RC);
109 Register FindUnusedReg(const TargetRegisterClass *RC) const;
141 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
158 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
|
| H A D | RegAllocCommon.h | 17 class TargetRegisterClass;
16 class TargetRegisterClass; global() variable
25 allocateAllRegClasses(const TargetRegisterInfo &,const TargetRegisterClass &) allocateAllRegClasses() argument
|
| H A D | FastISel.h | 57 class TargetRegisterClass; variable
392 const TargetRegisterClass *RC);
397 const TargetRegisterClass *RC, unsigned Op0);
402 const TargetRegisterClass *RC, unsigned Op0,
408 const TargetRegisterClass *RC, unsigned Op0,
414 const TargetRegisterClass *RC, unsigned Op0,
420 const TargetRegisterClass *RC, unsigned Op0,
426 const TargetRegisterClass *RC,
432 const TargetRegisterClass *RC, unsigned Op0,
438 const TargetRegisterClass *R
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 63 const TargetRegisterClass *
64 getMatchingSuperRegClass(const TargetRegisterClass *A,
65 const TargetRegisterClass *B,
68 const TargetRegisterClass *
69 getSubClassWithSubReg(const TargetRegisterClass *RC,
72 const TargetRegisterClass *
73 getLargestLegalSuperClass(const TargetRegisterClass *RC,
76 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
78 const TargetRegisterClass *SrcRC,
83 const TargetRegisterClass *
[all …]
|
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 191 const TargetRegisterClass *
192 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
198 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
208 const TargetRegisterClass *
215 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
216 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
226 const TargetRegisterClass * in getMinimalPhysRegClass()
233 const TargetRegisterClass *BestRC = nullptr; in getMinimalPhysRegClassLLT()
234 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT()
246 const TargetRegisterClass *R in getMinimalPhysRegClassLLT()
[all...] |
| H A D | CriticalAntiDepBreaker.cpp | 71 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
89 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
119 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
126 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
186 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction()
196 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
205 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
206 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
211 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) in PrescanInstruction()
239 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) { in PrescanInstruction()
[all …]
|
| H A D | MachineRegisterInfo.cpp | 59 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass()
69 static const TargetRegisterClass * in constrainRegClass()
71 const TargetRegisterClass *OldRC, in constrainRegClass()
72 const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
75 const TargetRegisterClass *NewRC = in constrainRegClass()
85 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( in constrainRegClass()
86 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
106 else if (isa<const TargetRegisterClass *>(RegCB) != in constrainRegAttrs()
107 isa<const TargetRegisterClass *>(ConstrainingRegCB)) in constrainRegAttrs()
109 else if (isa<const TargetRegisterClass *>(RegC in constrainRegAttrs()
[all...] |
| H A D | RegisterBank.cpp | 26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
|
| H A D | RegisterCoalescer.h | 22 class TargetRegisterClass; variable
57 const TargetRegisterClass *NewRC = nullptr;
109 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 23 class TargetRegisterClass; variable
63 const TargetRegisterClass *
64 getSubClassWithSubReg(const TargetRegisterClass *RC,
102 const TargetRegisterClass *
105 const TargetRegisterClass *
106 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
134 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
141 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
142 unsigned SubReg, const TargetRegisterClass *DstRC,
143 unsigned DstSubReg, const TargetRegisterClass *NewR
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.h | 60 const TargetRegisterClass *
69 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *getMaximalPhysRegClass(unsigned reg, MVT VT) const;
77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
101 const TargetRegisterClass *
102 getCrossCopyRegClass(const TargetRegisterClass *RC) const override { in getCrossCopyRegClass()
112 const TargetRegisterClass *intRegClass(unsigned Size) const;
|
| H A D | M68kRegisterInfo.cpp | 70 const TargetRegisterClass *
77 const TargetRegisterClass *RC) const { in getMatchingMegaReg()
84 const TargetRegisterClass *
91 const TargetRegisterClass *BestRC = nullptr; in getMaximalPhysRegClass()
94 const TargetRegisterClass *RC = *I; in getMaximalPhysRegClass()
107 const TargetRegisterClass &TRC) const { in getRegisterOrder()
267 const TargetRegisterClass *M68kRegisterInfo::intRegClass(unsigned size) const { in intRegClass()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 168 const TargetRegisterClass *
171 const TargetRegisterClass *
172 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
174 const TargetRegisterClass *
175 getLargestLegalSuperClass(const TargetRegisterClass *RC,
178 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
230 const TargetRegisterClass *SrcRC,
232 const TargetRegisterClass *DstRC,
234 const TargetRegisterClass *NewRC,
237 bool shouldRewriteCopySrc(const TargetRegisterClass *DefR
[all...] |
| H A D | ThumbRegisterInfo.h | 29 const TargetRegisterClass *
30 getLargestLegalSuperClass(const TargetRegisterClass *RC,
33 const TargetRegisterClass *
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
54 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
55 unsigned SubReg, const TargetRegisterClass *DstRC,
56 unsigned DstSubReg, const TargetRegisterClass *NewRC,
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
68 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
72 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *
|
| H A D | HexagonVLIWPacketizer.h | 25 class TargetRegisterClass; variable
123 const TargetRegisterClass *RC);
126 const TargetRegisterClass *RC);
131 const TargetRegisterClass *RC);
134 const TargetRegisterClass *RC);
146 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.h | 137 const TargetRegisterClass *
146 const TargetRegisterClass *
147 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
171 const TargetRegisterClass *SrcRC,
173 const TargetRegisterClass *DstRC,
175 const TargetRegisterClass *NewRC,
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterInfo.h | 25 class TargetRegisterClass; variable
47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
71 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRVVInitUndef.cpp | |