| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PostRASchedulerList.cpp | 76 class PostRAScheduler : public MachineFunctionPass { class
82 PostRAScheduler() : MachineFunctionPass(ID) {} in PostRAScheduler() function in __anon99a274ba0111::PostRAScheduler
108 char PostRAScheduler::ID = 0;
197 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
199 INITIALIZE_PASS(PostRAScheduler, DEBUG_TYPE,
262 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler()
277 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { in runOnMachineFunction()
307 LLVM_DEBUG(dbgs() << "PostRAScheduler\n"); in runOnMachineFunction()
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| H A D | TargetSubtargetInfo.cpp | 49 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kSchedule.td | 19 let PostRAScheduler = 0;
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiSchedule.td | 45 let PostRAScheduler = 0;
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSchedule.h | 309 bool PostRAScheduler; // default value is false member
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSubtarget.h | |
| H A D | RISCVSchedSiFiveP400.td | |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM4.td | 18 let PostRAScheduler = 1;
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| H A D | ARMScheduleM55.td | 89 let PostRAScheduler = 1;
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86Schedule.td | 736 // and disables PostRAScheduler.
742 let PostRAScheduler = 0;
748 // Define a model with the PostRAScheduler enabled.
750 let PostRAScheduler = 1;
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| H A D | X86ScheduleSLM.td | 21 let PostRAScheduler = 1;
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| H A D | X86ScheduleAtom.td | 28 let PostRAScheduler = 1;
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| H A D | X86ScheduleZnver3.td | 59 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
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| H A D | X86ScheduleBtVer2.td | 23 let PostRAScheduler = 1;
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| H A D | X86ScheduleZnver4.td | 55 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
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| H A D | X86ScheduleZnver1.td | 22 let PostRAScheduler = 1;
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| H A D | X86ScheduleZnver2.td | 22 let PostRAScheduler = 1;
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| H A D | X86ScheduleBdVer2.td | 29 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
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| H A D | X86.td | 1620 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SISchedule.td | 85 let PostRAScheduler = 1;
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| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 1475 bool PostRAScheduler = in EmitProcessorModels()
1476 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); in EmitProcessorModels()
1478 OS << " " << (PostRAScheduler ? "true" : "false") << ", // " in EmitProcessorModels()
1479 << "PostRAScheduler\n"; in EmitProcessorModels()
1456 bool PostRAScheduler = EmitProcessorModels() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedThunderX.td | 25 let PostRAScheduler = 1; // Use PostRA scheduler.
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| H A D | AArch64SchedA55.td | 29 let PostRAScheduler = 1; // Enable PostRA scheduler pass.
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSchedule.td | 88 bit PostRAScheduler = false; // Enable Post RegAlloc Scheduler pass.
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZScheduleZEC12.td | 24 let PostRAScheduler = 1;
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