1*04eeddc0SDimitry Andric//===-- M68kSchedule.td - M68k Scheduling Definitions ------*- tablegen -*-===// 2fe6060f1SDimitry Andric// 3fe6060f1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4fe6060f1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5fe6060f1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6fe6060f1SDimitry Andric// 7fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 8fe6060f1SDimitry Andric/// 9fe6060f1SDimitry Andric/// \file 10fe6060f1SDimitry Andric/// This file contains M68k scheduler definitions. 11fe6060f1SDimitry Andric/// 12fe6060f1SDimitry Andric//===----------------------------------------------------------------------===// 13fe6060f1SDimitry Andric 14fe6060f1SDimitry Andric/// This is a very general M68k Scheduling Model and best suited for the very 15fe6060f1SDimitry Andric/// first M68000 CPU, other model must override these characteristics 16fe6060f1SDimitry Andricclass M68kSchedModel : SchedMachineModel { 17fe6060f1SDimitry Andric let LoadLatency = 4; // Word (Rn) 18fe6060f1SDimitry Andric let HighLatency = 16; // Long ABS 19fe6060f1SDimitry Andric let PostRAScheduler = 0; 20fe6060f1SDimitry Andric let CompleteModel = 0; 21fe6060f1SDimitry Andric} 22fe6060f1SDimitry Andric 23fe6060f1SDimitry Andricdef GenericM68kModel : M68kSchedModel; 24