| /freebsd-src/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 112 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
114 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
117 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind"); in Decode_1000iiii_iiiiiiii()
159 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
161 SW.startLine() << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
162 (Opcode1 & 0xf0) ? "spare" : "pop "); in Decode_10110001_0000iiii()
163 if (((Opcode1 & 0xf0) == 0x00) && Opcode1) in Decode_10110001_0000iiii()
164 PrintGPR((Opcode1 & 0x0f)); in Decode_10110001_0000iiii()
187 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
188 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 146 unsigned Opcode1,
277 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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| H A D | X86TargetTransformInfo.cpp | 1519 unsigned Opcode1, const SmallBitVector &OpcodeMask, in getShuffleCost()
1521 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getShuffleCost()
6075 unsigned Opcode1, in areInlineCompatible()
6091 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in areInlineCompatible()
1464 getAltInstrCost(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask,TTI::TargetCostKind CostKind) const getAltInstrCost() argument
6003 isLegalAltInstr(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask) const isLegalAltInstr() argument
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| H A D | X86ISelLowering.cpp | 40376 unsigned Opcode1 = N1.getOpcode(); combineTargetShuffle() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 817 /// This function expectes two opcodes: \p Opcode1 and \p Opcode2 being
819 /// when \p Opcode0 is selected and `1` when Opcode1 is selected.
821 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1295 /// IR. This function expects two opcodes: \p Opcode1 and \p Opcode2 being
1297 /// when \p Opcode0 is selected and `1` when Opcode1 is selected.
1300 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1920 unsigned Opcode1,
2040 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
2435 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isFPVectorizationPotentiallyUnsafe()
2437 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMas in isFPVectorizationPotentiallyUnsafe()
2344 isLegalAltInstr(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask) isLegalAltInstr() argument
2593 getAltInstrCost(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask,TTI::TargetCostKind CostKind) getAltInstrCost() argument
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| H A D | TargetTransformInfoImpl.h | 313 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in hasVolatileVariant()
590 unsigned Opcode1, in getCastInstrCost()
300 isLegalAltInstr(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask) isLegalAltInstr() argument
569 getAltInstrCost(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask,TTI::TargetCostKind CostKind) getAltInstrCost() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 489 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
491 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in forceScalarizeMaskedScatter()
925 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in getCastContextHint()
928 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getCastContextHint()
475 isLegalAltInstr(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask) const isLegalAltInstr() argument
880 getAltInstrCost(VectorType * VecTy,unsigned Opcode0,unsigned Opcode1,const SmallBitVector & OpcodeMask,TTI::TargetCostKind CostKind) const getAltInstrCost() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 852 bool TargetInstrInfo::areOpcodesEqualOrInverse(unsigned Opcode1, in areOpcodesEqualOrInverse() argument
854 return Opcode1 == Opcode2 || getInverseOpcode(Opcode1) == Opcode2; in areOpcodesEqualOrInverse()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | Reassociate.cpp | 171 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
175 (BO->getOpcode() == Opcode1 || BO->getOpcode() == Opcode2)) in isReassociableOp()
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1265 /// Return true when \P Opcode1 or its inversion is equal to \P Opcode2.
1266 bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const; in accumulateInstrSeqToRootLatency()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 1032 /// Opcode1.
1034 unsigned Opcode1) {
1037 if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1) in doesRootHaveInTreeUses()
5274 unsigned Opcode1 = TE->getAltOpcode(); in getScalarsVectorizationState()
5275 SmallBitVector OpcodeMask(getAltInstrMask(TE->Scalars, Opcode0, Opcode1)); in getScalarsVectorizationState()
5277 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in getScalarsVectorizationState()
6185 unsigned Opcode1 = S.getAltOpcode(); in buildTree_rec()
6186 SmallBitVector OpcodeMask(getAltInstrMask(VL, Opcode0, Opcode1)); in buildTree_rec()
6189 Opcode0, Opcode1, OpcodeMask)) in buildTree_rec()
9979 unsigned Opcode1 in setInsertPointAfterBundle()
4348 unsigned Opcode1 = TE->getAltOpcode(); reorderTopToBottom() local
8466 unsigned Opcode1 = E->getAltOpcode(); getEntryCost() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4283 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterMemOps()
4292 int Scale1 = AArch64InstrInfo::getMemScale(Opcode1); in shouldClusterMemOps()
4224 shouldClusterFI(const MachineFrameInfo & MFI,int FI1,int64_t Offset1,unsigned Opcode1,int FI2,int64_t Offset2,unsigned Opcode2) shouldClusterFI() argument
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| H A D | AArch64ISelLowering.cpp | 17662 unsigned Opcode1 = SUB->getOperand(1).getOpcode(); in isConstantSplatVectorMaskForType()
17670 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in isConstantSplatVectorMaskForType()
17672 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in isConstantSplatVectorMaskForType()
16535 unsigned Opcode1 = SUB->getOperand(1).getOpcode(); performVecReduceAddCombineWithUADDLP() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5590 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); in isSaturatingMinMax()
5591 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
5593 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); isSaturatingMinMax() local
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