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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td61 foreach Lat = 3-20 in {
62 def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
63 let Latency = Lat;
68 foreach Lat = 4-16 in {
69 def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
70 let Latency = Lat;
241 foreach Lat = 3-20 in {
242 def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
243 let Latency = Lat; let NumMicroOps = 2;
268 foreach Lat = 4-16 in {
[all …]
H A DARMScheduleR52.td346 foreach Lat = 3-25 in {
347 def R52WriteILDM#Lat#Cy : SchedWriteRes<[R52UnitLd]> {
348 let Latency = Lat;
350 def R52WriteILDM#Lat#CyNo : SchedWriteRes<[]> {
351 let Latency = Lat;
546 foreach Lat = 1-32 in {
547 def R52WriteLM#Lat#Cy : SchedWriteRes<[]> {
548 let Latency = Lat;
H A DARMScheduleSwift.td382 foreach Lat = 3-25 in {
383 def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> {
384 let Latency = Lat;
386 def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> {
387 let Latency = Lat;
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp882 unsigned Lat = 0; in adjustSchedDependency()
885 Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *I); in adjustSchedDependency()
886 else if (Lat) in adjustSchedDependency()
887 --Lat; in adjustSchedDependency()
889 Dep.setLatency(Lat); in adjustSchedDependency()
895 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI);
896 for (++I; I != E && I->isBundledWithPred() && Lat; ++I) {
899 --Lat;
901 Dep.setLatency(Lat);
989 unsigned Lat in apply()
866 unsigned Lat = 0; adjustSchedDependency() local
879 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI); adjustSchedDependency() local
973 unsigned Lat = TSchedModel->computeInstrLatency(&MAI) - 1; apply() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleZnver3.td399 int Lat = 1, list<int> Res = [], int UOps = 1> {
401 let Latency = Lat;
408 list<ProcResourceKind> ExePorts, int Lat,
411 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
415 !add(Lat, LoadLat),
427 list<ProcResourceKind> ExePorts, int Lat = 1,
429 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
433 list<ProcResourceKind> ExePorts, int Lat = 1,
435 defm : __zn3WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
439 list<ProcResourceKind> ExePorts, int Lat
[all...]
H A DX86ScheduleZnver4.td396 int Lat = 1, list<int> Res = [], int UOps = 1> {
398 let Latency = Lat;
405 list<ProcResourceKind> ExePorts, int Lat,
408 defm : __Zn4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
412 !add(Lat, LoadLat),
424 list<ProcResourceKind> ExePorts, int Lat = 1,
426 defm : __Zn4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
430 list<ProcResourceKind> ExePorts, int Lat = 1,
432 defm : __Zn4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
436 list<ProcResourceKind> ExePorts, int Lat
[all...]
H A DX86ScheduleBdVer2.td191 list<ProcResourceKind> ExePorts, int Lat = 1,
194 let Latency = Lat;
201 list<ProcResourceKind> ExePorts, int Lat,
204 defm : PdWriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
208 !add(Lat, LoadLat),
219 list<ProcResourceKind> ExePorts, int Lat = 1,
222 defm : __pdWriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
227 list<ProcResourceKind> ExePorts, int Lat = 1,
230 defm : __pdWriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
235 list<ProcResourceKind> ExePorts, int Lat,
[all...]
H A DX86ScheduleBtVer2.td123 int Lat, list<int> Res = [], int UOps = 1,
127 let Latency = Lat;
135 let Latency = !add(Lat, 3);
143 int Lat, list<int> Res = [], int UOps = 1,
147 let Latency = Lat;
155 let Latency = !add(Lat, 5);
163 int Lat, list<int> Res = [2], int UOps = 2,
167 let Latency = Lat;
175 let Latency = !add(Lat, 5);
H A DX86ScheduleSLM.td64 int Lat, list<int> Res = [1], int UOps = 1,
68 let Latency = Lat;
76 let Latency = !add(Lat, LoadLat);
H A DX86ScheduleZnver1.td134 int Lat, list<int> Res = [], int UOps = 1,
138 let Latency = Lat;
146 let Latency = !add(Lat, LoadLat);
155 int Lat, list<int> Res = [], int UOps = 1,
159 let Latency = Lat;
167 let Latency = !add(Lat, LoadLat);
H A DX86ScheduleZnver2.td133 int Lat, list<int> Res = [], int UOps = 1,
137 let Latency = Lat;
145 let Latency = !add(Lat, LoadLat);
154 int Lat, list<int> Res = [], int UOps = 1,
158 let Latency = Lat;
166 let Latency = !add(Lat, LoadLat);
H A DX86SchedSandyBridge.td88 int Lat, list<int> Res = [1], int UOps = 1,
92 let Latency = Lat;
100 let Latency = !add(Lat, LoadLat);
H A DX86SchedSkylakeClient.td92 int Lat, list<int> Res = [1], int UOps = 1,
96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
H A DX86SchedBroadwell.td93 int Lat, list<int> Res = [1], int UOps = 1,
97 let Latency = Lat;
105 let Latency = !add(Lat, LoadLat);
H A DX86Schedule.td33 int Lat, list<int> Res, int UOps> {
35 let Latency = Lat;
H A DX86SchedHaswell.td98 int Lat, list<int> Res = [1], int UOps = 1,
102 let Latency = Lat;
110 let Latency = !add(Lat, LoadLat);
H A DX86SchedAlderlakeP.td107 int Lat, list<int> Res = [1], int UOps = 1,
111 let Latency = Lat;
119 let Latency = !add(Lat, LoadLat);
H A DX86SchedSkylakeServer.td92 int Lat, list<int> Res = [1], int UOps = 1,
96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
H A DX86SchedIceLake.td99 int Lat, list<int> Res = [1], int UOps = 1,
103 let Latency = Lat;
111 let Latency = !add(Lat, LoadLat);
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp603 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) in restoreLatency()
609 I.setLatency(Lat); in changeLatency()
615 F->setLatency(Lat); in changeLatency()
H A DHexagonSubtarget.h352 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h147 void setLatency(unsigned Lat) { in setLatency() argument
148 Latency = Lat; in setLatency()
/freebsd-src/contrib/ntp/ntpd/
H A Drefclock_oncore.c3121 double Lat, Lon, Ht; in oncore_get_timestamp() local
3128 Lat = lat; in oncore_get_timestamp()
3132 Lat /= 3600000; in oncore_get_timestamp()
3137 "Ga Posn Lat = %.7f, Lon = %.7f, Ht = %.2f", Lat, in oncore_get_timestamp()
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp1643 unsigned Lat = D.getLatency(); in createAdjacencyStructure()
1646 Dep.setLatency(Lat);
1583 unsigned Lat = D.getLatency(); swapAntiDependences() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td1310 (instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"),

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