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Searched refs:opcode (Results 1 – 25 of 69) sorted by relevance

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/dpdk/drivers/common/dpaax/caamflib/rta/
H A Dfifo_load_store_cmd.h51 uint32_t opcode = 0; in rta_fifo_load() local
59 opcode = CMD_SEQ_FIFO_LOAD; in rta_fifo_load()
62 opcode = CMD_FIFO_LOAD; in rta_fifo_load()
102 opcode |= val; in rta_fifo_load()
105 opcode |= FIFOLD_CLASS_CLASS1; in rta_fifo_load()
107 opcode |= FIFOLD_CLASS_CLASS2; in rta_fifo_load()
109 opcode |= FIFOLD_CLASS_BOTH; in rta_fifo_load()
113 opcode |= FIFOLD_TYPE_FLUSH1; in rta_fifo_load()
115 opcode |= FIFOLD_TYPE_LAST1; in rta_fifo_load()
117 opcode |= FIFOLD_TYPE_LAST2; in rta_fifo_load()
[all …]
H A Dheader_cmd.h46 uint32_t opcode = CMD_SHARED_DESC_HDR; in rta_shr_header() local
57 opcode |= HDR_SHARE_ALWAYS; in rta_shr_header()
60 opcode |= HDR_SHARE_SERIAL; in rta_shr_header()
69 opcode |= HDR_SHARE_WAIT; in rta_shr_header()
77 opcode |= HDR_ONE; in rta_shr_header()
79 opcode |= (start_idx << HDR_START_IDX_SHIFT) & in rta_shr_header()
82 opcode |= (start_idx << HDR_START_IDX_SHIFT) & in rta_shr_header()
86 opcode |= HDR_DNR; in rta_shr_header()
88 opcode |= HDR_CLEAR_IFIFO; in rta_shr_header()
90 opcode |= HDR_SAVECTX; in rta_shr_header()
[all …]
H A Dkey_cmd.h31 uint32_t opcode = 0; in rta_key() local
43 opcode = CMD_SEQ_KEY; in rta_key()
46 opcode = CMD_KEY; in rta_key()
103 opcode |= KEY_DEST_CLASS1; in rta_key()
106 opcode |= KEY_DEST_CLASS2; in rta_key()
109 opcode |= KEY_DEST_CLASS1 | KEY_DEST_PKHA_E; in rta_key()
112 opcode |= KEY_DEST_CLASS1 | KEY_DEST_AFHA_SBOX; in rta_key()
115 opcode |= KEY_DEST_CLASS2 | KEY_DEST_MDHA_SPLIT; in rta_key()
125 opcode |= length; in rta_key()
133 opcode |= KEY_ENC; in rta_key()
[all …]
H A Dseq_in_out_ptr_cmd.h44 uint32_t opcode = CMD_SEQ_IN_PTR; in rta_seq_in_ptr() local
73 opcode |= SQIN_RBS; in rta_seq_in_ptr()
75 opcode |= SQIN_INL; in rta_seq_in_ptr()
77 opcode |= SQIN_SGF; in rta_seq_in_ptr()
79 opcode |= SQIN_PRE; in rta_seq_in_ptr()
81 opcode |= SQIN_RTO; in rta_seq_in_ptr()
83 opcode |= SQIN_RJD; in rta_seq_in_ptr()
85 opcode |= SQIN_SOP; in rta_seq_in_ptr()
92 opcode |= SQIN_EXT; in rta_seq_in_ptr()
94 opcode |= length & SQIN_LEN_MASK; in rta_seq_in_ptr()
[all …]
H A Djump_cmd.h56 uint32_t opcode = CMD_JUMP; in rta_jump() local
68 opcode |= JUMP_TYPE_HALT; in rta_jump()
71 opcode |= JUMP_TYPE_HALT_USER; in rta_jump()
74 opcode |= JUMP_TYPE_NONLOCAL; in rta_jump()
77 opcode |= JUMP_TYPE_GOSUB; in rta_jump()
80 opcode |= JUMP_TYPE_RETURN; in rta_jump()
83 opcode |= JUMP_TYPE_LOCAL_INC; in rta_jump()
86 opcode |= JUMP_TYPE_LOCAL_DEC; in rta_jump()
102 opcode |= JUMP_TEST_INVALL; in rta_jump()
105 opcode |= JUMP_TEST_ANY; in rta_jump()
[all …]
H A Dmath_cmd.h83 uint32_t opcode = CMD_MATH; in rta_math() local
124 opcode |= MATH_SRC0_IMM; in rta_math()
134 opcode |= val; in rta_math()
139 opcode |= MATH_SRC1_IMM; in rta_math()
149 opcode |= val; in rta_math()
160 opcode |= val; in rta_math()
181 opcode |= op; in rta_math()
190 opcode |= (options & ~(IMMED | IMMED2)); in rta_math()
195 opcode |= MATH_LEN_1BYTE; in rta_math()
198 opcode |= MATH_LEN_2BYTE; in rta_math()
[all …]
H A Dsec_run_time_asm.h666 uint32_t opcode; in rta_patch_move() local
672 opcode = bswap ? swab32(program->buffer[line]) : program->buffer[line]; in rta_patch_move()
674 opcode &= (uint32_t)~MOVE_OFFSET_MASK; in rta_patch_move()
675 opcode |= (new_ref << (MOVE_OFFSET_SHIFT + 2)) & MOVE_OFFSET_MASK; in rta_patch_move()
676 program->buffer[line] = bswap ? swab32(opcode) : opcode; in rta_patch_move()
684 uint32_t opcode; in rta_patch_jmp() local
690 opcode = bswap ? swab32(program->buffer[line]) : program->buffer[line]; in rta_patch_jmp()
692 opcode &= (uint32_t)~JUMP_OFFSET_MASK; in rta_patch_jmp()
693 opcode |= (new_ref - (line + program->start_pc)) & JUMP_OFFSET_MASK; in rta_patch_jmp()
694 program->buffer[line] = bswap ? swab32(opcode) : opcode; in rta_patch_jmp()
[all …]
H A Dmove_cmd.h91 uint32_t opcode = 0; in rta_move() local
100 opcode = CMD_MOVEB; in rta_move()
102 opcode = CMD_MOVEDW; in rta_move()
112 opcode = CMD_MOVE_LEN; in rta_move()
115 opcode = CMD_MOVE; in rta_move()
127 opcode |= (offset << MOVE_OFFSET_SHIFT) & MOVE_OFFSET_MASK; in rta_move()
131 opcode |= ((src_offset / 16) << MOVE_AUX_SHIFT) & MOVE_AUX_MASK; in rta_move()
133 opcode |= ((dst_offset / 16) << MOVE_AUX_SHIFT) & MOVE_AUX_MASK; in rta_move()
135 opcode |= MOVE_AUX_LS; in rta_move()
150 opcode |= (uint32_t)ret; in rta_move()
[all …]
H A Dstore_cmd.h66 uint32_t opcode = 0, val; in rta_store() local
71 opcode = CMD_SEQ_STORE; in rta_store()
73 opcode = CMD_STORE; in rta_store()
96 opcode |= LDST_IMM; in rta_store()
99 opcode |= LDST_VLF; in rta_store()
116 opcode |= val; in rta_store()
122 opcode |= (length >> 2); in rta_store()
123 opcode |= (uint32_t)((offset >> 2) << LDST_OFFSET_SHIFT); in rta_store()
125 opcode |= length; in rta_store()
126 opcode |= (uint32_t)(offset << LDST_OFFSET_SHIFT); in rta_store()
[all …]
H A Dload_cmd.h218 uint32_t opcode = 0; in rta_load() local
223 opcode = CMD_SEQ_LOAD; in rta_load()
225 opcode = CMD_LOAD; in rta_load()
233 opcode |= LDST_SGF; in rta_load()
235 opcode |= LDST_VLF; in rta_load()
255 opcode |= LDST_IMM; in rta_load()
269 opcode |= load_dst[pos].dst_opcode; in rta_load()
273 opcode |= (length >> 2); in rta_load()
274 opcode |= ((offset >> 2) << LDST_OFFSET_SHIFT); in rta_load()
276 opcode |= length; in rta_load()
[all …]
H A Dnfifo_cmd.h99 uint32_t opcode = 0, val; in rta_nfifo_load() local
112 opcode |= val; in rta_nfifo_load()
121 opcode |= val; in rta_nfifo_load()
125 opcode |= length & NFIFOENTRY_DLEN_MASK; in rta_nfifo_load()
133 &opcode); in rta_nfifo_load()
138 nfifo_pad_flags_sz[rta_sec_era], &opcode); in rta_nfifo_load()
142 __rta_out32(program, opcode); in rta_nfifo_load()
H A Dsignature_cmd.h14 uint32_t opcode = CMD_SIGNATURE; in rta_signature() local
24 opcode |= sign_type; in rta_signature()
31 __rta_out32(program, opcode); in rta_signature()
/dpdk/drivers/net/ionic/
H A Dionic_dev.c45 ionic_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode); in ionic_dev_cmd_go()
60 .identify.opcode = IONIC_CMD_IDENTIFY, in ionic_dev_cmd_identify()
71 .init.opcode = IONIC_CMD_INIT, in ionic_dev_cmd_init()
82 .reset.opcode = IONIC_CMD_RESET, in ionic_dev_cmd_reset()
94 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, in ionic_dev_cmd_port_identify()
105 .port_init.opcode = IONIC_CMD_PORT_INIT, in ionic_dev_cmd_port_init()
117 .port_reset.opcode = IONIC_CMD_PORT_RESET, in ionic_dev_cmd_port_reset()
128 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, in ionic_dev_cmd_port_state()
141 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, in ionic_dev_cmd_port_speed()
154 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, in ionic_dev_cmd_port_mtu()
[all …]
H A Dionic_main.c65 ionic_opcode_to_str(enum ionic_cmd_opcode opcode) in ionic_opcode_to_str() argument
67 switch (opcode) { in ionic_opcode_to_str()
131 name = ionic_opcode_to_str(ctx->cmd.cmd.opcode); in ionic_adminq_check_err()
137 ctx->cmd.cmd.opcode, in ionic_adminq_check_err()
143 IONIC_PRINT(DEBUG, "%s (%d) succeeded", name, ctx->cmd.cmd.opcode); in ionic_adminq_check_err()
290 ionic_opcode_to_str(ctx->cmd.cmd.opcode), ctx->cmd.cmd.opcode); in ionic_adminq_post_wait()
295 ctx->cmd.cmd.opcode, err); in ionic_adminq_post_wait()
327 ioread8(&idev->dev_cmd->cmd.cmd.opcode), in ionic_dev_cmd_wait()
338 ioread8(&idev->dev_cmd->cmd.cmd.opcode), in ionic_dev_cmd_wait()
H A Dionic_rxtx_simple.c84 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; in ionic_tx() local
95 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; in ionic_tx()
103 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; in ionic_tx()
107 if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE) in ionic_tx()
124 cmd = encode_txq_desc_cmd(opcode, flags, 0, addr); in ionic_tx()
H A Dionic_rxtx_sg.c93 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; in ionic_tx_sg() local
102 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; in ionic_tx_sg()
110 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; in ionic_tx_sg()
114 if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE) in ionic_tx_sg()
131 cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr); in ionic_tx_sg()
/dpdk/drivers/crypto/ionic/
H A Dionic_crypto_cmds.c69 iocpt_opcode_to_str(enum iocpt_cmd_opcode opcode) in iocpt_opcode_to_str() argument
71 switch (opcode) { in iocpt_opcode_to_str()
110 iocpt_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode); in iocpt_dev_cmd_go()
133 ioread8(&dev->dev_cmd->cmd.cmd.opcode), in iocpt_dev_cmd_wait()
144 ioread8(&dev->dev_cmd->cmd.cmd.opcode), elapsed_usec); in iocpt_dev_cmd_wait()
185 .reset.opcode = IOCPT_CMD_RESET, in iocpt_dev_cmd_reset()
195 .lif_identify.opcode = IOCPT_CMD_LIF_IDENTIFY, in iocpt_dev_cmd_lif_identify()
207 .lif_init.opcode = IOCPT_CMD_LIF_INIT, in iocpt_dev_cmd_lif_init()
219 .lif_reset.opcode = IOCPT_CMD_LIF_RESET, in iocpt_dev_cmd_lif_reset()
230 .q_identify.opcode = IOCPT_CMD_Q_IDENTIFY, in iocpt_dev_cmd_queue_identify()
[all …]
/dpdk/drivers/net/hns3/
H A Dhns3_mbx.c338 uint8_t opcode; in hns3_handle_mbx_msg_out_intr() local
346 opcode = req->msg.code & 0xff; in hns3_handle_mbx_msg_out_intr()
352 if (crq->desc[next_to_use].opcode == 0) in hns3_handle_mbx_msg_out_intr()
355 if (opcode == HNS3_MBX_PF_VF_RESP) { in hns3_handle_mbx_msg_out_intr()
361 crq->desc[next_to_use].opcode = 0; in hns3_handle_mbx_msg_out_intr()
430 uint8_t opcode; in hns3vf_handle_mbx_msg() local
467 opcode = req->msg.code & 0xff; in hns3vf_handle_mbx_msg()
473 opcode); in hns3vf_handle_mbx_msg()
481 if (desc->opcode == 0) { in hns3vf_handle_mbx_msg()
488 switch (opcode) { in hns3vf_handle_mbx_msg()
[all …]
/dpdk/drivers/net/qede/base/
H A Decore_hw.c482 u32 opcode = 0; in ecore_dmae_opcode() local
488 opcode |= (is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie) << in ecore_dmae_opcode()
492 opcode |= (src_pf_id & DMAE_CMD_SRC_PF_ID_MASK) << in ecore_dmae_opcode()
496 opcode |= (is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie) << in ecore_dmae_opcode()
500 opcode |= (dst_pf_id & DMAE_CMD_DST_PF_ID_MASK) << in ecore_dmae_opcode()
510 opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT; in ecore_dmae_opcode()
511 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT; in ecore_dmae_opcode()
514 opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT; in ecore_dmae_opcode()
519 opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT; in ecore_dmae_opcode()
523 opcode |= port_id << DMAE_CMD_PORT_ID_SHIFT; in ecore_dmae_opcode()
[all …]
/dpdk/drivers/common/idpf/base/
H A Didpf_controlq_api.h50 u16 opcode; member
58 #define FILL_OPCODE_V1(msg, opcode) ((msg).cookie.cfg.mbx.chnl_opcode = opcode) argument
H A Didpf_controlq.c76 desc->opcode = 0; in idpf_ctlq_init_rxq_bufs()
310 desc->opcode = CPU_TO_LE16(msg->opcode); in idpf_ctlq_send()
339 if (msg->opcode == idpf_mbq_opc_send_msg_to_pf) { in idpf_ctlq_send()
351 if (msg->opcode == idpf_mbq_opc_send_msg_to_pf) { in idpf_ctlq_send()
675 q_msg[i].opcode = LE16_TO_CPU(desc->opcode); in idpf_ctlq_recv()
/dpdk/drivers/net/cxgbe/base/
H A Dt4_msg.h53 __u8 opcode; member
62 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) argument
78 __u8 opcode; member
419 __u8 opcode; member
546 u8 opcode; member
555 u8 opcode; member
/dpdk/lib/net/
H A Drte_higig.h115 uint16_t opcode:3;
125 uint16_t opcode:3;
119 uint16_t opcode:3; global() member
129 uint16_t opcode:3; global() member
H A Drte_ib.h26 uint8_t opcode; /**< Opcode. */
30 uint8_t opcode; /**< Opcode. */ global() member
/dpdk/drivers/regex/mlx5/
H A Dmlx5_regex_devx.c23 MLX5_SET(set_regexp_params_in, in, opcode, MLX5_CMD_SET_REGEX_PARAMS); in mlx5_devx_regex_rules_program()

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