xref: /dpdk/drivers/common/dpaax/caamflib/rta/store_cmd.h (revision c0ded849131598760a25e96ff368d035838af0b3)
1*c0ded849SHemant Agrawal /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2*c0ded849SHemant Agrawal  *
3*c0ded849SHemant Agrawal  * Copyright 2008-2016 Freescale Semiconductor Inc.
4*c0ded849SHemant Agrawal  * Copyright 2016,2019 NXP
5*c0ded849SHemant Agrawal  */
6*c0ded849SHemant Agrawal 
7*c0ded849SHemant Agrawal #ifndef __RTA_STORE_CMD_H__
8*c0ded849SHemant Agrawal #define __RTA_STORE_CMD_H__
9*c0ded849SHemant Agrawal 
10*c0ded849SHemant Agrawal extern enum rta_sec_era rta_sec_era;
11*c0ded849SHemant Agrawal 
12*c0ded849SHemant Agrawal static const uint32_t store_src_table[][2] = {
13*c0ded849SHemant Agrawal /*1*/	{ KEY1SZ,       LDST_CLASS_1_CCB | LDST_SRCDST_WORD_KEYSZ_REG },
14*c0ded849SHemant Agrawal 	{ KEY2SZ,       LDST_CLASS_2_CCB | LDST_SRCDST_WORD_KEYSZ_REG },
15*c0ded849SHemant Agrawal 	{ DJQDA,        LDST_CLASS_DECO | LDST_SRCDST_WORD_DECO_JQDAR },
16*c0ded849SHemant Agrawal 	{ MODE1,        LDST_CLASS_1_CCB | LDST_SRCDST_WORD_MODE_REG },
17*c0ded849SHemant Agrawal 	{ MODE2,        LDST_CLASS_2_CCB | LDST_SRCDST_WORD_MODE_REG },
18*c0ded849SHemant Agrawal 	{ DJQCTRL,      LDST_CLASS_DECO | LDST_SRCDST_WORD_DECO_JQCTRL },
19*c0ded849SHemant Agrawal 	{ DATA1SZ,      LDST_CLASS_1_CCB | LDST_SRCDST_WORD_DATASZ_REG },
20*c0ded849SHemant Agrawal 	{ DATA2SZ,      LDST_CLASS_2_CCB | LDST_SRCDST_WORD_DATASZ_REG },
21*c0ded849SHemant Agrawal 	{ DSTAT,        LDST_CLASS_DECO | LDST_SRCDST_WORD_DECO_STAT },
22*c0ded849SHemant Agrawal 	{ ICV1SZ,       LDST_CLASS_1_CCB | LDST_SRCDST_WORD_ICVSZ_REG },
23*c0ded849SHemant Agrawal 	{ ICV2SZ,       LDST_CLASS_2_CCB | LDST_SRCDST_WORD_ICVSZ_REG },
24*c0ded849SHemant Agrawal 	{ DPID,         LDST_CLASS_DECO | LDST_SRCDST_WORD_PID },
25*c0ded849SHemant Agrawal 	{ CCTRL,        LDST_SRCDST_WORD_CHACTRL },
26*c0ded849SHemant Agrawal 	{ ICTRL,        LDST_SRCDST_WORD_IRQCTRL },
27*c0ded849SHemant Agrawal 	{ CLRW,         LDST_SRCDST_WORD_CLRW },
28*c0ded849SHemant Agrawal 	{ MATH0,        LDST_CLASS_DECO | LDST_SRCDST_WORD_DECO_MATH0 },
29*c0ded849SHemant Agrawal 	{ CSTAT,        LDST_SRCDST_WORD_STAT },
30*c0ded849SHemant Agrawal 	{ MATH1,        LDST_CLASS_DECO | LDST_SRCDST_WORD_DECO_MATH1 },
31*c0ded849SHemant Agrawal 	{ MATH2,        LDST_CLASS_DECO | LDST_SRCDST_WORD_DECO_MATH2 },
32*c0ded849SHemant Agrawal 	{ AAD1SZ,       LDST_CLASS_1_CCB | LDST_SRCDST_WORD_DECO_AAD_SZ },
33*c0ded849SHemant Agrawal 	{ MATH3,        LDST_CLASS_DECO | LDST_SRCDST_WORD_DECO_MATH3 },
34*c0ded849SHemant Agrawal 	{ IV1SZ,        LDST_CLASS_1_CCB | LDST_SRCDST_WORD_CLASS1_IV_SZ },
35*c0ded849SHemant Agrawal 	{ PKASZ,        LDST_CLASS_1_CCB | LDST_SRCDST_WORD_PKHA_A_SZ },
36*c0ded849SHemant Agrawal 	{ PKBSZ,        LDST_CLASS_1_CCB | LDST_SRCDST_WORD_PKHA_B_SZ },
37*c0ded849SHemant Agrawal 	{ PKESZ,        LDST_CLASS_1_CCB | LDST_SRCDST_WORD_PKHA_E_SZ },
38*c0ded849SHemant Agrawal 	{ PKNSZ,        LDST_CLASS_1_CCB | LDST_SRCDST_WORD_PKHA_N_SZ },
39*c0ded849SHemant Agrawal 	{ CONTEXT1,     LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_CONTEXT },
40*c0ded849SHemant Agrawal 	{ CONTEXT2,     LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT },
41*c0ded849SHemant Agrawal 	{ DESCBUF,      LDST_CLASS_DECO | LDST_SRCDST_WORD_DESCBUF },
42*c0ded849SHemant Agrawal /*30*/	{ JOBDESCBUF,   LDST_CLASS_DECO | LDST_SRCDST_WORD_DESCBUF_JOB },
43*c0ded849SHemant Agrawal 	{ SHAREDESCBUF, LDST_CLASS_DECO | LDST_SRCDST_WORD_DESCBUF_SHARED },
44*c0ded849SHemant Agrawal /*32*/	{ JOBDESCBUF_EFF,   LDST_CLASS_DECO |
45*c0ded849SHemant Agrawal 		LDST_SRCDST_WORD_DESCBUF_JOB_WE },
46*c0ded849SHemant Agrawal 	{ SHAREDESCBUF_EFF, LDST_CLASS_DECO |
47*c0ded849SHemant Agrawal 		LDST_SRCDST_WORD_DESCBUF_SHARED_WE },
48*c0ded849SHemant Agrawal /*34*/	{ GTR,          LDST_CLASS_DECO | LDST_SRCDST_WORD_GTR },
49*c0ded849SHemant Agrawal 	{ STR,          LDST_CLASS_DECO | LDST_SRCDST_WORD_STR }
50*c0ded849SHemant Agrawal };
51*c0ded849SHemant Agrawal 
52*c0ded849SHemant Agrawal /*
53*c0ded849SHemant Agrawal  * Allowed STORE sources for each SEC ERA.
54*c0ded849SHemant Agrawal  * Values represent the number of entries from source_src_table[] that are
55*c0ded849SHemant Agrawal  * supported.
56*c0ded849SHemant Agrawal  */
57*c0ded849SHemant Agrawal static const unsigned int store_src_table_sz[] = {29, 31, 33, 33,
58*c0ded849SHemant Agrawal 						  33, 33, 35, 35,
59*c0ded849SHemant Agrawal 						  35, 35};
60*c0ded849SHemant Agrawal 
61*c0ded849SHemant Agrawal static inline int
rta_store(struct program * program,uint64_t src,uint16_t offset,uint64_t dst,uint32_t length,uint32_t flags)62*c0ded849SHemant Agrawal rta_store(struct program *program, uint64_t src,
63*c0ded849SHemant Agrawal 	  uint16_t offset, uint64_t dst, uint32_t length,
64*c0ded849SHemant Agrawal 	  uint32_t flags)
65*c0ded849SHemant Agrawal {
66*c0ded849SHemant Agrawal 	uint32_t opcode = 0, val;
67*c0ded849SHemant Agrawal 	int ret = -EINVAL;
68*c0ded849SHemant Agrawal 	unsigned int start_pc = program->current_pc;
69*c0ded849SHemant Agrawal 
70*c0ded849SHemant Agrawal 	if (flags & SEQ)
71*c0ded849SHemant Agrawal 		opcode = CMD_SEQ_STORE;
72*c0ded849SHemant Agrawal 	else
73*c0ded849SHemant Agrawal 		opcode = CMD_STORE;
74*c0ded849SHemant Agrawal 
75*c0ded849SHemant Agrawal 	/* parameters check */
76*c0ded849SHemant Agrawal 	if ((flags & IMMED) && (flags & SGF)) {
77*c0ded849SHemant Agrawal 		pr_err("STORE: Invalid flag. SEC PC: %d; Instr: %d\n",
78*c0ded849SHemant Agrawal 		       program->current_pc, program->current_instruction);
79*c0ded849SHemant Agrawal 		goto err;
80*c0ded849SHemant Agrawal 	}
81*c0ded849SHemant Agrawal 	if ((flags & IMMED) && (offset != 0)) {
82*c0ded849SHemant Agrawal 		pr_err("STORE: Invalid flag. SEC PC: %d; Instr: %d\n",
83*c0ded849SHemant Agrawal 		       program->current_pc, program->current_instruction);
84*c0ded849SHemant Agrawal 		goto err;
85*c0ded849SHemant Agrawal 	}
86*c0ded849SHemant Agrawal 
87*c0ded849SHemant Agrawal 	if ((flags & SEQ) && ((src == JOBDESCBUF) || (src == SHAREDESCBUF) ||
88*c0ded849SHemant Agrawal 			      (src == JOBDESCBUF_EFF) ||
89*c0ded849SHemant Agrawal 			      (src == SHAREDESCBUF_EFF))) {
90*c0ded849SHemant Agrawal 		pr_err("STORE: Invalid SRC type. SEC PC: %d; Instr: %d\n",
91*c0ded849SHemant Agrawal 		       program->current_pc, program->current_instruction);
92*c0ded849SHemant Agrawal 		goto err;
93*c0ded849SHemant Agrawal 	}
94*c0ded849SHemant Agrawal 
95*c0ded849SHemant Agrawal 	if (flags & IMMED)
96*c0ded849SHemant Agrawal 		opcode |= LDST_IMM;
97*c0ded849SHemant Agrawal 
98*c0ded849SHemant Agrawal 	if ((flags & SGF) || (flags & VLF))
99*c0ded849SHemant Agrawal 		opcode |= LDST_VLF;
100*c0ded849SHemant Agrawal 
101*c0ded849SHemant Agrawal 	/*
102*c0ded849SHemant Agrawal 	 * source for data to be stored can be specified as:
103*c0ded849SHemant Agrawal 	 *    - register location; set in src field[9-15];
104*c0ded849SHemant Agrawal 	 *    - if IMMED flag is set, data is set in value field [0-31];
105*c0ded849SHemant Agrawal 	 *      user can give this value as actual value or pointer to data
106*c0ded849SHemant Agrawal 	 */
107*c0ded849SHemant Agrawal 	if (!(flags & IMMED)) {
108*c0ded849SHemant Agrawal 		ret = __rta_map_opcode((uint32_t)src, store_src_table,
109*c0ded849SHemant Agrawal 				       store_src_table_sz[rta_sec_era], &val);
110*c0ded849SHemant Agrawal 		if (ret < 0) {
111*c0ded849SHemant Agrawal 			pr_err("STORE: Invalid source. SEC PC: %d; Instr: %d\n",
112*c0ded849SHemant Agrawal 			       program->current_pc,
113*c0ded849SHemant Agrawal 			       program->current_instruction);
114*c0ded849SHemant Agrawal 			goto err;
115*c0ded849SHemant Agrawal 		}
116*c0ded849SHemant Agrawal 		opcode |= val;
117*c0ded849SHemant Agrawal 	}
118*c0ded849SHemant Agrawal 
119*c0ded849SHemant Agrawal 	/* DESC BUFFER: length / offset values are specified in 4-byte words */
120*c0ded849SHemant Agrawal 	if ((src == DESCBUF) || (src == JOBDESCBUF) || (src == SHAREDESCBUF) ||
121*c0ded849SHemant Agrawal 	    (src == JOBDESCBUF_EFF) || (src == SHAREDESCBUF_EFF)) {
122*c0ded849SHemant Agrawal 		opcode |= (length >> 2);
123*c0ded849SHemant Agrawal 		opcode |= (uint32_t)((offset >> 2) << LDST_OFFSET_SHIFT);
124*c0ded849SHemant Agrawal 	} else {
125*c0ded849SHemant Agrawal 		opcode |= length;
126*c0ded849SHemant Agrawal 		opcode |= (uint32_t)(offset << LDST_OFFSET_SHIFT);
127*c0ded849SHemant Agrawal 	}
128*c0ded849SHemant Agrawal 
129*c0ded849SHemant Agrawal 	__rta_out32(program, opcode);
130*c0ded849SHemant Agrawal 	program->current_instruction++;
131*c0ded849SHemant Agrawal 
132*c0ded849SHemant Agrawal 	if ((src == JOBDESCBUF) || (src == SHAREDESCBUF) ||
133*c0ded849SHemant Agrawal 	    (src == JOBDESCBUF_EFF) || (src == SHAREDESCBUF_EFF))
134*c0ded849SHemant Agrawal 		return (int)start_pc;
135*c0ded849SHemant Agrawal 
136*c0ded849SHemant Agrawal 	/* for STORE, a pointer to where the data will be stored if needed */
137*c0ded849SHemant Agrawal 	if (!(flags & SEQ))
138*c0ded849SHemant Agrawal 		__rta_out64(program, program->ps, dst);
139*c0ded849SHemant Agrawal 
140*c0ded849SHemant Agrawal 	/* for IMMED data, place the data here */
141*c0ded849SHemant Agrawal 	if (flags & IMMED)
142*c0ded849SHemant Agrawal 		__rta_inline_data(program, src, flags & __COPY_MASK, length);
143*c0ded849SHemant Agrawal 
144*c0ded849SHemant Agrawal 	return (int)start_pc;
145*c0ded849SHemant Agrawal 
146*c0ded849SHemant Agrawal  err:
147*c0ded849SHemant Agrawal 	program->first_error_pc = start_pc;
148*c0ded849SHemant Agrawal 	program->current_instruction++;
149*c0ded849SHemant Agrawal 	return ret;
150*c0ded849SHemant Agrawal }
151*c0ded849SHemant Agrawal 
152*c0ded849SHemant Agrawal #endif /* __RTA_STORE_CMD_H__ */
153