| /dflybsd-src/sys/dev/drm/radeon/ |
| H A D | rv770_dpm.h | 180 u32 engine_clock,
183 u32 engine_clock, u32 memory_clock,
201 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
204 u32 engine_clock, u32 memory_clock,
226 u32 engine_clock);
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| H A D | rv740_dpm.c | 121 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, in rv740_populate_sclk_value() argument
138 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
161 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
177 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
188 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
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| H A D | rv730_dpm.c | 41 u32 engine_clock, in rv730_populate_sclk_value() argument
58 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
93 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
109 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
120 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
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| H A D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
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| H A D | rv770_dpm.c | 391 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
489 u32 engine_clock, in rv770_populate_sclk_value() argument
511 engine_clock, false, ÷rs); in rv770_populate_sclk_value()
522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
544 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
560 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
727 u32 engine_clock) in rv770_calculate_memory_refresh_rate() argument
738 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in rv770_calculate_memory_refresh_rate()
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| H A D | ci_dpm.c | 2530 const u32 engine_clock, in ci_register_patching_mc_arb() argument
2544 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; in ci_register_patching_mc_arb()
2548 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; in ci_register_patching_mc_arb()
3194 u32 engine_clock, in ci_calculate_sclk_params() argument
3210 engine_clock, false, ÷rs); in ci_calculate_sclk_params()
3223 u32 vco_freq = engine_clock * dividers.post_div; in ci_calculate_sclk_params()
3239 sclk->SclkFrequency = engine_clock; in ci_calculate_sclk_params()
3250 u32 engine_clock, in ci_populate_single_graphic_level() argument
3257 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3263 engine_clock, &graphic_level->MinVddc); in ci_populate_single_graphic_level()
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| H A D | ni_dpm.c | 1997 u32 engine_clock, in ni_calculate_sclk_params() argument
2016 engine_clock, false, ÷rs); in ni_calculate_sclk_params()
2023 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2040 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2056 sclk->sclk_value = engine_clock; in ni_calculate_sclk_params()
2068 u32 engine_clock, in ni_populate_sclk_value() argument
2074 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in ni_populate_sclk_value()
2159 u32 engine_clock, in ni_populate_mclk_value() argument
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| H A D | si_dpm.c | 1758 u32 engine_clock,
4273 u32 engine_clock) in si_calculate_memory_refresh_rate() argument
4286 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
4781 u32 engine_clock, in si_calculate_sclk_params() argument
4800 engine_clock, false, ÷rs); in si_calculate_sclk_params()
4806 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
4823 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
4839 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
4851 u32 engine_clock, in si_populate_sclk_value() argument
4857 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
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| H A D | cypress_dpm.c | 474 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument
904 u32 engine_clock, u32 memory_clock) in cypress_calculate_burst_time() argument
908 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2); in cypress_calculate_burst_time()
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| H A D | rv6xx_dpm.c | 783 u32 engine_clock) in calculate_memory_refresh_rate() argument
792 return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in calculate_memory_refresh_rate()
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| /dflybsd-src/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | smu7_hwmgr.c | 2920 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) in smu7_apply_state_adjust_rules()
2921 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()
2964 sclk = smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
2979 smu7_ps->performance_levels[0].engine_clock = sclk; in smu7_apply_state_adjust_rules()
2982 smu7_ps->performance_levels[1].engine_clock = in smu7_apply_state_adjust_rules()
2983 (smu7_ps->performance_levels[1].engine_clock >= in smu7_apply_state_adjust_rules()
2984 smu7_ps->performance_levels[0].engine_clock) ? in smu7_apply_state_adjust_rules()
2985 smu7_ps->performance_levels[1].engine_clock : in smu7_apply_state_adjust_rules()
2986 smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3004 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()
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| H A D | ppatomctrl.h | 295 …t_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_in…
297 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, ui…
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| H A D | smu10_hwmgr.h | 76 uint32_t engine_clock; member
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| H A D | smu10_hwmgr.c | 723 smu10_ps->levels[index].engine_clock = 0; in smu10_dpm_get_pp_table_entry_callback()
929 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
930 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1… in smu10_get_current_shallow_sleep_clocks()
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| H A D | smu7_hwmgr.h | 56 uint32_t engine_clock; member
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| H A D | ppatomctrl.c | 175 uint32_t engine_clock, in atomctrl_set_engine_dram_timings_rv770() argument
184 cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) | in atomctrl_set_engine_dram_timings_rv770()
1291 const uint32_t engine_clock, in atomctrl_get_engine_clock_spread_spectrum() argument
1295 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo); in atomctrl_get_engine_clock_spread_spectrum()
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| /dflybsd-src/sys/dev/drm/amd/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 796 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) in iceland_calculate_sclk_params() argument
811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in iceland_calculate_sclk_params()
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
863 sclk->SclkFrequency = engine_clock; in iceland_calculate_sclk_params()
892 uint32_t engine_clock, in iceland_populate_single_graphic_level() argument
898 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in iceland_populate_single_graphic_level()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
908 graphic_level->SclkFrequency = engine_clock; in iceland_populate_single_graphic_level()
914 engine_clock, in iceland_populate_single_graphic_level()
937 smu7_get_sleep_divider_id_from_clock(engine_clock, in iceland_populate_single_graphic_level()
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| H A D | tonga_smumgr.c | 529 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) in tonga_calculate_sclk_params() argument
544 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
575 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
596 sclk->SclkFrequency = engine_clock; in tonga_calculate_sclk_params()
607 uint32_t engine_clock, in tonga_populate_single_graphic_level() argument
617 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in tonga_populate_single_graphic_level()
626 vdd_dep_table, engine_clock, in tonga_populate_single_graphic_level()
633 graphic_level->SclkFrequency = engine_clock; in tonga_populate_single_graphic_level()
654 smu7_get_sleep_divider_id_from_clock(engine_clock, in tonga_populate_single_graphic_level()
1449 uint32_t engine_clock, in tonga_populate_memory_timing_parameters() argument
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| H A D | ci_smumgr.c | 1620 uint32_t engine_clock, in ci_populate_memory_timing_parameters() argument
1631 engine_clock, memory_clock); in ci_populate_memory_timing_parameters()
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| /dflybsd-src/sys/dev/drm/amd/amdgpu/ |
| H A D | si_dpm.c | 1848 u32 engine_clock,
4738 u32 engine_clock) in si_calculate_memory_refresh_rate() argument
4751 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
5244 u32 engine_clock, in si_calculate_sclk_params() argument
5263 engine_clock, false, ÷rs); in si_calculate_sclk_params()
5269 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
5286 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
5302 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
5314 u32 engine_clock, in si_populate_sclk_value() argument
5320 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
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