1*57e252bfSMichael Neumann /* 2*57e252bfSMichael Neumann * Copyright 2011 Advanced Micro Devices, Inc. 3*57e252bfSMichael Neumann * 4*57e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 5*57e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 6*57e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 7*57e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*57e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 9*57e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 10*57e252bfSMichael Neumann * 11*57e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 12*57e252bfSMichael Neumann * all copies or substantial portions of the Software. 13*57e252bfSMichael Neumann * 14*57e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*57e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*57e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*57e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*57e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*57e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*57e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 21*57e252bfSMichael Neumann * 22*57e252bfSMichael Neumann */ 23*57e252bfSMichael Neumann #ifndef __CYPRESS_DPM_H__ 24*57e252bfSMichael Neumann #define __CYPRESS_DPM_H__ 25*57e252bfSMichael Neumann 26*57e252bfSMichael Neumann #include "rv770_dpm.h" 27*57e252bfSMichael Neumann #include "evergreen_smc.h" 28*57e252bfSMichael Neumann 29*57e252bfSMichael Neumann struct evergreen_mc_reg_entry { 30*57e252bfSMichael Neumann u32 mclk_max; 31*57e252bfSMichael Neumann u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 32*57e252bfSMichael Neumann }; 33*57e252bfSMichael Neumann 34*57e252bfSMichael Neumann struct evergreen_mc_reg_table { 35*57e252bfSMichael Neumann u8 last; 36*57e252bfSMichael Neumann u8 num_entries; 37*57e252bfSMichael Neumann u16 valid_flag; 38*57e252bfSMichael Neumann struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 39*57e252bfSMichael Neumann SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 40*57e252bfSMichael Neumann }; 41*57e252bfSMichael Neumann 42*57e252bfSMichael Neumann struct evergreen_ulv_param { 43*57e252bfSMichael Neumann bool supported; 44*57e252bfSMichael Neumann struct rv7xx_pl *pl; 45*57e252bfSMichael Neumann }; 46*57e252bfSMichael Neumann 47*57e252bfSMichael Neumann struct evergreen_arb_registers { 48*57e252bfSMichael Neumann u32 mc_arb_dram_timing; 49*57e252bfSMichael Neumann u32 mc_arb_dram_timing2; 50*57e252bfSMichael Neumann u32 mc_arb_rfsh_rate; 51*57e252bfSMichael Neumann u32 mc_arb_burst_time; 52*57e252bfSMichael Neumann }; 53*57e252bfSMichael Neumann 54*57e252bfSMichael Neumann struct at { 55*57e252bfSMichael Neumann u32 rlp; 56*57e252bfSMichael Neumann u32 rmp; 57*57e252bfSMichael Neumann u32 lhp; 58*57e252bfSMichael Neumann u32 lmp; 59*57e252bfSMichael Neumann }; 60*57e252bfSMichael Neumann 61*57e252bfSMichael Neumann struct evergreen_power_info { 62*57e252bfSMichael Neumann /* must be first! */ 63*57e252bfSMichael Neumann struct rv7xx_power_info rv7xx; 64*57e252bfSMichael Neumann /* flags */ 65*57e252bfSMichael Neumann bool vddci_control; 66*57e252bfSMichael Neumann bool dynamic_ac_timing; 67*57e252bfSMichael Neumann bool abm; 68*57e252bfSMichael Neumann bool mcls; 69*57e252bfSMichael Neumann bool light_sleep; 70*57e252bfSMichael Neumann bool memory_transition; 71*57e252bfSMichael Neumann bool pcie_performance_request; 72*57e252bfSMichael Neumann bool pcie_performance_request_registered; 73*57e252bfSMichael Neumann bool sclk_deep_sleep; 74*57e252bfSMichael Neumann bool dll_default_on; 75*57e252bfSMichael Neumann bool ls_clock_gating; 76*57e252bfSMichael Neumann bool smu_uvd_hs; 77*57e252bfSMichael Neumann bool uvd_enabled; 78*57e252bfSMichael Neumann /* stored values */ 79*57e252bfSMichael Neumann u16 acpi_vddci; 80*57e252bfSMichael Neumann u8 mvdd_high_index; 81*57e252bfSMichael Neumann u8 mvdd_low_index; 82*57e252bfSMichael Neumann u32 mclk_edc_wr_enable_threshold; 83*57e252bfSMichael Neumann struct evergreen_mc_reg_table mc_reg_table; 84*57e252bfSMichael Neumann struct atom_voltage_table vddc_voltage_table; 85*57e252bfSMichael Neumann struct atom_voltage_table vddci_voltage_table; 86*57e252bfSMichael Neumann struct evergreen_arb_registers bootup_arb_registers; 87*57e252bfSMichael Neumann struct evergreen_ulv_param ulv; 88*57e252bfSMichael Neumann struct at ats[2]; 89*57e252bfSMichael Neumann /* smc offsets */ 90*57e252bfSMichael Neumann u16 mc_reg_table_start; 91*57e252bfSMichael Neumann struct radeon_ps current_rps; 92*57e252bfSMichael Neumann struct rv7xx_ps current_ps; 93*57e252bfSMichael Neumann struct radeon_ps requested_rps; 94*57e252bfSMichael Neumann struct rv7xx_ps requested_ps; 95*57e252bfSMichael Neumann }; 96*57e252bfSMichael Neumann 97*57e252bfSMichael Neumann #define CYPRESS_HASI_DFLT 400000 98*57e252bfSMichael Neumann #define CYPRESS_MGCGTTLOCAL0_DFLT 0x00000000 99*57e252bfSMichael Neumann #define CYPRESS_MGCGTTLOCAL1_DFLT 0x00000000 100*57e252bfSMichael Neumann #define CYPRESS_MGCGTTLOCAL2_DFLT 0x00000000 101*57e252bfSMichael Neumann #define CYPRESS_MGCGTTLOCAL3_DFLT 0x00000000 102*57e252bfSMichael Neumann #define CYPRESS_MGCGCGTSSMCTRL_DFLT 0x81944bc0 103*57e252bfSMichael Neumann #define REDWOOD_MGCGCGTSSMCTRL_DFLT 0x6e944040 104*57e252bfSMichael Neumann #define CEDAR_MGCGCGTSSMCTRL_DFLT 0x46944040 105*57e252bfSMichael Neumann #define CYPRESS_VRC_DFLT 0xC00033 106*57e252bfSMichael Neumann 107*57e252bfSMichael Neumann #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 108*57e252bfSMichael Neumann #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 109*57e252bfSMichael Neumann #define PCIE_PERF_REQ_PECI_GEN1 2 110*57e252bfSMichael Neumann #define PCIE_PERF_REQ_PECI_GEN2 3 111*57e252bfSMichael Neumann #define PCIE_PERF_REQ_PECI_GEN3 4 112*57e252bfSMichael Neumann 113*57e252bfSMichael Neumann int cypress_convert_power_level_to_smc(struct radeon_device *rdev, 114*57e252bfSMichael Neumann struct rv7xx_pl *pl, 115*57e252bfSMichael Neumann RV770_SMC_HW_PERFORMANCE_LEVEL *level, 116*57e252bfSMichael Neumann u8 watermark_level); 117*57e252bfSMichael Neumann int cypress_populate_smc_acpi_state(struct radeon_device *rdev, 118*57e252bfSMichael Neumann RV770_SMC_STATETABLE *table); 119*57e252bfSMichael Neumann int cypress_populate_smc_voltage_tables(struct radeon_device *rdev, 120*57e252bfSMichael Neumann RV770_SMC_STATETABLE *table); 121*57e252bfSMichael Neumann int cypress_populate_smc_initial_state(struct radeon_device *rdev, 122*57e252bfSMichael Neumann struct radeon_ps *radeon_initial_state, 123*57e252bfSMichael Neumann RV770_SMC_STATETABLE *table); 124*57e252bfSMichael Neumann u32 cypress_calculate_burst_time(struct radeon_device *rdev, 125*57e252bfSMichael Neumann u32 engine_clock, u32 memory_clock); 126*57e252bfSMichael Neumann void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev, 127*57e252bfSMichael Neumann struct radeon_ps *radeon_new_state, 128*57e252bfSMichael Neumann struct radeon_ps *radeon_current_state); 129*57e252bfSMichael Neumann int cypress_upload_sw_state(struct radeon_device *rdev, 130*57e252bfSMichael Neumann struct radeon_ps *radeon_new_state); 131*57e252bfSMichael Neumann int cypress_upload_mc_reg_table(struct radeon_device *rdev, 132*57e252bfSMichael Neumann struct radeon_ps *radeon_new_state); 133*57e252bfSMichael Neumann void cypress_program_memory_timing_parameters(struct radeon_device *rdev, 134*57e252bfSMichael Neumann struct radeon_ps *radeon_new_state); 135*57e252bfSMichael Neumann void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 136*57e252bfSMichael Neumann struct radeon_ps *radeon_new_state, 137*57e252bfSMichael Neumann struct radeon_ps *radeon_current_state); 138*57e252bfSMichael Neumann int cypress_construct_voltage_tables(struct radeon_device *rdev); 139*57e252bfSMichael Neumann int cypress_get_mvdd_configuration(struct radeon_device *rdev); 140*57e252bfSMichael Neumann void cypress_enable_spread_spectrum(struct radeon_device *rdev, 141*57e252bfSMichael Neumann bool enable); 142*57e252bfSMichael Neumann void cypress_enable_display_gap(struct radeon_device *rdev); 143*57e252bfSMichael Neumann int cypress_get_table_locations(struct radeon_device *rdev); 144*57e252bfSMichael Neumann int cypress_populate_mc_reg_table(struct radeon_device *rdev, 145*57e252bfSMichael Neumann struct radeon_ps *radeon_boot_state); 146*57e252bfSMichael Neumann void cypress_program_response_times(struct radeon_device *rdev); 147*57e252bfSMichael Neumann int cypress_notify_smc_display_change(struct radeon_device *rdev, 148*57e252bfSMichael Neumann bool has_display); 149*57e252bfSMichael Neumann void cypress_enable_sclk_control(struct radeon_device *rdev, 150*57e252bfSMichael Neumann bool enable); 151*57e252bfSMichael Neumann void cypress_enable_mclk_control(struct radeon_device *rdev, 152*57e252bfSMichael Neumann bool enable); 153*57e252bfSMichael Neumann void cypress_start_dpm(struct radeon_device *rdev); 154*57e252bfSMichael Neumann void cypress_advertise_gen2_capability(struct radeon_device *rdev); 155*57e252bfSMichael Neumann u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); 156*57e252bfSMichael Neumann u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, 157*57e252bfSMichael Neumann u32 memory_clock, bool strobe_mode); 158*57e252bfSMichael Neumann u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk); 159*57e252bfSMichael Neumann 160*57e252bfSMichael Neumann #endif 161