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Searched refs:SM (Results 1 – 25 of 87) sorted by relevance

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/dflybsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_aic.c453 ahp->ah_aic_sram[i] = (SM(aic_sram[i].sram.vga_dir_sign, in ar9300_aic_cal_post_process()
455 SM(aic_sram[i].sram.vga_quad_sign, in ar9300_aic_cal_post_process()
457 SM(aic_sram[i].sram.com_att_6db, in ar9300_aic_cal_post_process()
459 SM(aic_sram[i].sram.valid, in ar9300_aic_cal_post_process()
461 SM(aic_sram[i].sram.rot_dir_att_db, in ar9300_aic_cal_post_process()
463 SM(aic_sram[i].sram.rot_quad_att_db, in ar9300_aic_cal_post_process()
525 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9300_aic_calibration()
526 SM(40, AR_PHY_AIC_CAL_MAX_HOP_COUNT) | in ar9300_aic_calibration()
527 SM(1, AR_PHY_AIC_CAL_MIN_VALID_COUNT) | //26 in ar9300_aic_calibration()
528 SM(37, AR_PHY_AIC_F_WLAN) | in ar9300_aic_calibration()
[all …]
H A Dar9300_radar.c241 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
245 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
249 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
256 val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
259 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
262 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
267 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
275 val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN);
279 val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH);
283 val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH);
[all …]
H A Dar9300_xmit.c72 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG)); in ar9300_update_tx_trig_level()
235 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK)); in set_tx_q_interrupts()
237 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR) in set_tx_q_interrupts()
238 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in set_tx_q_interrupts()
326 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN) in ar9300_reset_tx_queue()
327 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) in ar9300_reset_tx_queue()
328 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ar9300_reset_tx_queue()
333 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | in ar9300_reset_tx_queue()
334 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | in ar9300_reset_tx_queue()
335 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); in ar9300_reset_tx_queue()
[all …]
H A Dar9300_mci.c948 regval = SM(1, AR_BTCOEX_CTRL_JUPITER_MODE) | in ar9300_mci_reset()
949 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9300_mci_reset()
950 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9300_mci_reset()
951 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9300_mci_reset()
952 SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) | in ar9300_mci_reset()
953 SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) | in ar9300_mci_reset()
954 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | in ar9300_mci_reset()
955 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) | in ar9300_mci_reset()
956 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); in ar9300_mci_reset()
959 regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10); in ar9300_mci_reset()
[all …]
H A Dar9300_xmit_ds.c112 ads->ds_ctl17 = __bswap32(SM(key_type, AR_encr_type)); in ar9300_fill_tx_desc()
116 ads->ds_ctl17 = SM(key_type, AR_encr_type); in ar9300_fill_tx_desc()
126 ads->ds_ctl17 = SM(key_type, AR_encr_type); in ar9300_fill_tx_desc()
567 ads->ds_ctl12 |= SM((1 << chain_num), AR_paprd_chain_mask); in ar9300_set_paprd_tx_desc()
607 | SM(tx_power, AR_xmit_power0) in ar9300_set_11n_tx_desc()
614 (key_ix != HAL_TXKEYIX_INVALID ? SM(key_ix, AR_dest_idx) : 0) in ar9300_set_11n_tx_desc()
615 | SM(type, AR_frame_type) in ar9300_set_11n_tx_desc()
621 SM(key_type, AR_encr_type) | (flags & HAL_TXDESC_LDPC ? AR_ldpc : 0); in ar9300_set_11n_tx_desc()
757 | SM(0, AR_burst_dur); in ar9300_set_11n_rate_scenario()
774 | SM(rts_cts_rate, AR_rts_cts_rate); in ar9300_set_11n_rate_scenario()
[all …]
H A Dar9300_timer.c148 (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | in ar9300_start_generic_timer()
149 SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); in ar9300_start_generic_timer()
168 (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | in ar9300_stop_generic_timer()
169 SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); in ar9300_stop_generic_timer()
H A Dar9300_spectral.c82 val |= SM(MAX_RADAR_RSSI_THRESH, AR_PHY_RADAR_0_RRSSI); in ar9300_disable_radar()
85 val |= SM(MAX_RADAR_HEIGHT, AR_PHY_RADAR_0_HEIGHT); in ar9300_disable_radar()
114 val |= SM(MAX_RADAR_DC_PWR_THRESH, AR_PHY_RADAR_DC_PWR_THRESH); in ar9300_set_radar_dc_thresh()
341 val |= SM(ss->ss_fft_period, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD); in ar9300_configure_spectral_scan()
346 val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); in ar9300_configure_spectral_scan()
356 val |= SM(0, AR_PHY_SPECTRAL_SCAN_COUNT); in ar9300_configure_spectral_scan()
358 val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT); in ar9300_configure_spectral_scan()
364 val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); in ar9300_configure_spectral_scan()
/dflybsd-src/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_xmit.c79 SM(10, AR_QUIET2_QUIET_DUR)); in ar5416StopTxDma()
125 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
128 (SM((_series)[_index].Rate, AR_XmitRate##_index))
131 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
139 |SM((_series)[_index].ChSel, AR_ChainSel##_index)
372 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0) in ar5416SetupTxDesc()
380 ads->ds_ctl7 = SM(ahp->ah_tx_chainmask, AR_ChainSel0) in ar5416SetupTxDesc()
381 | SM(ahp->ah_tx_chainmask, AR_ChainSel1) in ar5416SetupTxDesc()
382 | SM(ahp->ah_tx_chainmask, AR_ChainSel2) in ar5416SetupTxDesc()
383 | SM(ahp->ah_tx_chainmask, AR_ChainSel3) in ar5416SetupTxDesc()
[all …]
H A Dar5416_btcoex.c66 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | in ar5416BTCoexConfig()
67 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | in ar5416BTCoexConfig()
68 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | in ar5416BTCoexConfig()
69 SM(btconf->bt_mode, AR_BT_MODE) | in ar5416BTCoexConfig()
70 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | in ar5416BTCoexConfig()
71 SM(rxClearPolarity, AR_BT_RX_CLEAR_POLARITY) | in ar5416BTCoexConfig()
72 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | in ar5416BTCoexConfig()
73 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); in ar5416BTCoexConfig()
75 ahp->ah_btCoexMode2 |= SM(btconf->bt_hold_rxclear, in ar5416BTCoexConfig()
89 ahp->ah_btCoexMode |= SM(qnum, AR_BT_QCU_THRESH); in ar5416BTCoexSetQcuThresh()
[all …]
H A Dar5416_spectral.c58 val |= SM(MAX_RADAR_RSSI_THRESH, AR_PHY_RADAR_0_RRSSI); in ar5416DisableRadar()
61 val |= SM(MAX_RADAR_HEIGHT, AR_PHY_RADAR_0_HEIGHT); in ar5416DisableRadar()
94 val |= SM(ss->ss_fft_period, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD); in ar5416ConfigureSpectralScan()
99 val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); in ar5416ConfigureSpectralScan()
104 val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); in ar5416ConfigureSpectralScan()
111 val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT); in ar5416ConfigureSpectralScan()
128 val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT_KIWI); in ar5416ConfigureSpectralScan()
H A Dar5416_radar.c131 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR); in ar5416EnableDfs()
135 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI); in ar5416EnableDfs()
139 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT); in ar5416EnableDfs()
143 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); in ar5416EnableDfs()
147 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND); in ar5416EnableDfs()
178 val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH); in ar5416EnableDfs()
184 val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH); in ar5416EnableDfs()
205 val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN); in ar5416EnableDfs()
H A Dar5416_reset.c439 powerVal = SM(ackTpcPow, AR_TPC_ACK) |
440 SM(ctsTpcPow, AR_TPC_CTS) |
441 SM(chirpTpcPow, AR_TPC_CHIRP);
599 SM(ahp->ah_txTrigLev, AR_FTRIG)); in ar5416InitDMA()
711 SM(2, AR_NOACK_2BIT_VALUE) | in ar5416InitQoS()
712 SM(5, AR_NOACK_BIT_OFFSET) | in ar5416InitQoS()
713 SM(0, AR_NOACK_BYTE_OFFSET)); in ar5416InitQoS()
1354 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); in ar5416SetReset()
1506 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5416InitPLL()
1508 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5416InitPLL()
[all …]
/dflybsd-src/sys/dev/netif/ath/ath_hal/ar9002/
H A Dar9285_diversity.c91 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); in ar9285SetAntennaSwitch()
96 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285SetAntennaSwitch()
97 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285SetAntennaSwitch()
98 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9285SetAntennaSwitch()
99 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); in ar9285SetAntennaSwitch()
105 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285SetAntennaSwitch()
106 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285SetAntennaSwitch()
107 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9285SetAntennaSwitch()
108 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_MAIN_GAINTB); in ar9285SetAntennaSwitch()
114 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285SetAntennaSwitch()
[all …]
H A Dar9287_reset.c499 SM(pModal->iqCalICh[i], in ar9287SetBoardValues()
501 SM(pModal->iqCalQCh[i], in ar9287SetBoardValues()
531 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ar9287SetBoardValues()
532 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) in ar9287SetBoardValues()
533 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) in ar9287SetBoardValues()
534 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); in ar9287SetBoardValues()
551 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | in ar9287SetBoardValues()
552 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | in ar9287SetBoardValues()
553 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | in ar9287SetBoardValues()
554 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | in ar9287SetBoardValues()
[all …]
H A Dar9285_btcoex.c114 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); in ar9285BTCoexAntennaDiversity()
115 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285BTCoexAntennaDiversity()
116 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285BTCoexAntennaDiversity()
117 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9285BTCoexAntennaDiversity()
118 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); in ar9285BTCoexAntennaDiversity()
123 regVal |= SM((ant_div_control1 >> 3), in ar9285BTCoexAntennaDiversity()
H A Dar9280_attach.c107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL()
118 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL()
120 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL()
122 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL()
125 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL()
127 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL()
129 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL()
131 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL()
133 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL()
670 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar9280SpurMitigate()
[all …]
/dflybsd-src/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212_xmit.c71 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG)); in ar5212UpdateTxTrigLevel()
216 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) in setTxQInterrupts()
217 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC) in setTxQInterrupts()
220 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) in setTxQInterrupts()
221 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL) in setTxQInterrupts()
308 SM(cwMin, AR_D_LCL_IFS_CWMIN) in ar5212ResetTxQueue()
309 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) in ar5212ResetTxQueue()
310 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ar5212ResetTxQueue()
314 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) in ar5212ResetTxQueue()
315 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) in ar5212ResetTxQueue()
[all …]
H A Dar5212_beacon.c187 | SM(bs->bs_intval, AR_BEACON_PERIOD) in ar5212SetStaBeaconTimers()
188 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) in ar5212SetStaBeaconTimers()
198 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR); in ar5212SetStaBeaconTimers()
252 SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM) in ar5212SetStaBeaconTimers()
253 | SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT) in ar5212SetStaBeaconTimers()
258 SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM) in ar5212SetStaBeaconTimers()
259 | SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT) in ar5212SetStaBeaconTimers()
262 SM(beaconintval, AR_SLEEP3_TIM_PERIOD) in ar5212SetStaBeaconTimers()
263 | SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD) in ar5212SetStaBeaconTimers()
H A Dar2317.c510 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5), in ar2317SetPowerTable()
530 | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN); in ar2317SetPowerTable()
534 tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3); in ar2317SetPowerTable()
538 tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2); in ar2317SetPowerTable()
542 tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1); in ar2317SetPowerTable()
576 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | in ar2317SetPowerTable()
577 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | in ar2317SetPowerTable()
578 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | in ar2317SetPowerTable()
579 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | in ar2317SetPowerTable()
580 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); in ar2317SetPowerTable()
H A Dar2413.c530 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5), in ar2413SetPowerTable()
550 | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN); in ar2413SetPowerTable()
554 tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3); in ar2413SetPowerTable()
558 tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2); in ar2413SetPowerTable()
562 tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1); in ar2413SetPowerTable()
596 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | in ar2413SetPowerTable()
597 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | in ar2413SetPowerTable()
598 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | in ar2413SetPowerTable()
599 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | in ar2413SetPowerTable()
600 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); in ar2413SetPowerTable()
H A Dar2316.c532 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5), in ar2316SetPowerTable()
552 | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN); in ar2316SetPowerTable()
556 tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3); in ar2316SetPowerTable()
560 tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2); in ar2316SetPowerTable()
564 tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1); in ar2316SetPowerTable()
598 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | in ar2316SetPowerTable()
599 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | in ar2316SetPowerTable()
600 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | in ar2316SetPowerTable()
601 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | in ar2316SetPowerTable()
602 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); in ar2316SetPowerTable()
/dflybsd-src/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211_xmit.c183 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) in setTxQInterrupts()
184 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC) in setTxQInterrupts()
187 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) in setTxQInterrupts()
188 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL) in setTxQInterrupts()
269 SM(cwMin, AR_D_LCL_IFS_CWMIN) in ar5211ResetTxQueue()
270 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) in ar5211ResetTxQueue()
271 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ar5211ResetTxQueue()
275 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) in ar5211ResetTxQueue()
276 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) in ar5211ResetTxQueue()
277 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG) in ar5211ResetTxQueue()
[all …]
/dflybsd-src/sys/dev/netif/ath/ath_hal/ar5312/
H A Dar5312_reset.c243 SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) | in ar5312Reset()
244 SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) | in ar5312Reset()
257 SM((ee->ee_cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) | in ar5312Reset()
258 SM((cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX)); in ar5312Reset()
289 SM(2, AR_PHY_SIGMA_DELTA_ADC_SEL) | in ar5312Reset()
290 SM(4, AR_PHY_SIGMA_DELTA_FILT2) | in ar5312Reset()
291 SM(0x16, AR_PHY_SIGMA_DELTA_FILT1) | in ar5312Reset()
292 SM(0, AR_PHY_SIGMA_DELTA_ADC_CLIP)); in ar5312Reset()
541 SM(2, AR_NOACK_2BIT_VALUE) | in ar5312Reset()
542 SM(5, AR_NOACK_BIT_OFFSET) | in ar5312Reset()
[all …]
/dflybsd-src/sys/dev/netif/ath/ath_hal/ar9001/
H A Dar9160_attach.c92 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9160InitPLL()
95 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9160InitPLL()
97 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9160InitPLL()
100 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL()
102 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL()
104 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL()
/dflybsd-src/sys/bus/u4b/wlan/
H A Dif_urtwn.c1652 SM(R92C_LSSI_PARAM_ADDR, addr) | in urtwn_r92c_rf_write()
1653 SM(R92C_LSSI_PARAM_DATA, val)); in urtwn_r92c_rf_write()
1661 SM(R88E_LSSI_PARAM_ADDR, addr) | in urtwn_r88e_rf_write()
1662 SM(R92C_LSSI_PARAM_DATA, val)); in urtwn_r88e_rf_write()
1701 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | in urtwn_llt_write()
1702 SM(R92C_LLT_INIT_ADDR, addr) | in urtwn_llt_write()
1703 SM(R92C_LLT_INIT_DATA, data)); in urtwn_llt_write()
2128 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | in urtwn_init_beacon()
2131 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | in urtwn_init_beacon()
2132 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); in urtwn_init_beacon()
[all …]

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