1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #include "opt_ah.h"
20572ff6f6SMatthew Dillon
21572ff6f6SMatthew Dillon #include "ah.h"
22572ff6f6SMatthew Dillon #include "ah_internal.h"
23572ff6f6SMatthew Dillon
24572ff6f6SMatthew Dillon #include "ar5212/ar5212.h"
25572ff6f6SMatthew Dillon #include "ar5212/ar5212reg.h"
26572ff6f6SMatthew Dillon #include "ar5212/ar5212phy.h"
27572ff6f6SMatthew Dillon
28572ff6f6SMatthew Dillon #include "ah_eeprom_v3.h"
29572ff6f6SMatthew Dillon
30572ff6f6SMatthew Dillon #define AH_5212_2317
31572ff6f6SMatthew Dillon #include "ar5212/ar5212.ini"
32572ff6f6SMatthew Dillon
33572ff6f6SMatthew Dillon #define N(a) (sizeof(a)/sizeof(a[0]))
34572ff6f6SMatthew Dillon
35572ff6f6SMatthew Dillon typedef RAW_DATA_STRUCT_2413 RAW_DATA_STRUCT_2317;
36572ff6f6SMatthew Dillon typedef RAW_DATA_PER_CHANNEL_2413 RAW_DATA_PER_CHANNEL_2317;
37572ff6f6SMatthew Dillon #define PWR_TABLE_SIZE_2317 PWR_TABLE_SIZE_2413
38572ff6f6SMatthew Dillon
39572ff6f6SMatthew Dillon struct ar2317State {
40572ff6f6SMatthew Dillon RF_HAL_FUNCS base; /* public state, must be first */
41572ff6f6SMatthew Dillon uint16_t pcdacTable[PWR_TABLE_SIZE_2317];
42572ff6f6SMatthew Dillon
43572ff6f6SMatthew Dillon uint32_t Bank1Data[N(ar5212Bank1_2317)];
44572ff6f6SMatthew Dillon uint32_t Bank2Data[N(ar5212Bank2_2317)];
45572ff6f6SMatthew Dillon uint32_t Bank3Data[N(ar5212Bank3_2317)];
46572ff6f6SMatthew Dillon uint32_t Bank6Data[N(ar5212Bank6_2317)];
47572ff6f6SMatthew Dillon uint32_t Bank7Data[N(ar5212Bank7_2317)];
48572ff6f6SMatthew Dillon
49572ff6f6SMatthew Dillon /*
50572ff6f6SMatthew Dillon * Private state for reduced stack usage.
51572ff6f6SMatthew Dillon */
52572ff6f6SMatthew Dillon /* filled out Vpd table for all pdGains (chanL) */
53572ff6f6SMatthew Dillon uint16_t vpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL]
54572ff6f6SMatthew Dillon [MAX_PWR_RANGE_IN_HALF_DB];
55572ff6f6SMatthew Dillon /* filled out Vpd table for all pdGains (chanR) */
56572ff6f6SMatthew Dillon uint16_t vpdTable_R[MAX_NUM_PDGAINS_PER_CHANNEL]
57572ff6f6SMatthew Dillon [MAX_PWR_RANGE_IN_HALF_DB];
58572ff6f6SMatthew Dillon /* filled out Vpd table for all pdGains (interpolated) */
59572ff6f6SMatthew Dillon uint16_t vpdTable_I[MAX_NUM_PDGAINS_PER_CHANNEL]
60572ff6f6SMatthew Dillon [MAX_PWR_RANGE_IN_HALF_DB];
61572ff6f6SMatthew Dillon };
62572ff6f6SMatthew Dillon #define AR2317(ah) ((struct ar2317State *) AH5212(ah)->ah_rfHal)
63572ff6f6SMatthew Dillon
64572ff6f6SMatthew Dillon extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
65572ff6f6SMatthew Dillon uint32_t numBits, uint32_t firstBit, uint32_t column);
66572ff6f6SMatthew Dillon
67572ff6f6SMatthew Dillon static void
ar2317WriteRegs(struct ath_hal * ah,u_int modesIndex,u_int freqIndex,int writes)68572ff6f6SMatthew Dillon ar2317WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
69572ff6f6SMatthew Dillon int writes)
70572ff6f6SMatthew Dillon {
71572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2317, modesIndex, writes);
72572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212Common_2317, 1, writes);
73572ff6f6SMatthew Dillon HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2317, freqIndex, writes);
74572ff6f6SMatthew Dillon }
75572ff6f6SMatthew Dillon
76572ff6f6SMatthew Dillon /*
77572ff6f6SMatthew Dillon * Take the MHz channel value and set the Channel value
78572ff6f6SMatthew Dillon *
79572ff6f6SMatthew Dillon * ASSUMES: Writes enabled to analog bus
80572ff6f6SMatthew Dillon */
81572ff6f6SMatthew Dillon static HAL_BOOL
ar2317SetChannel(struct ath_hal * ah,const struct ieee80211_channel * chan)82572ff6f6SMatthew Dillon ar2317SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
83572ff6f6SMatthew Dillon {
84572ff6f6SMatthew Dillon uint16_t freq = ath_hal_gethwchannel(ah, chan);
85572ff6f6SMatthew Dillon uint32_t channelSel = 0;
86572ff6f6SMatthew Dillon uint32_t bModeSynth = 0;
87572ff6f6SMatthew Dillon uint32_t aModeRefSel = 0;
88572ff6f6SMatthew Dillon uint32_t reg32 = 0;
89572ff6f6SMatthew Dillon
90572ff6f6SMatthew Dillon OS_MARK(ah, AH_MARK_SETCHANNEL, freq);
91572ff6f6SMatthew Dillon
92572ff6f6SMatthew Dillon if (freq < 4800) {
93572ff6f6SMatthew Dillon uint32_t txctl;
94572ff6f6SMatthew Dillon channelSel = freq - 2272 ;
95572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(channelSel, 8);
96572ff6f6SMatthew Dillon
97572ff6f6SMatthew Dillon txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
98572ff6f6SMatthew Dillon if (freq == 2484) {
99572ff6f6SMatthew Dillon /* Enable channel spreading for channel 14 */
100572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
101572ff6f6SMatthew Dillon txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
102572ff6f6SMatthew Dillon } else {
103572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
104572ff6f6SMatthew Dillon txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
105572ff6f6SMatthew Dillon }
106572ff6f6SMatthew Dillon } else if ((freq % 20) == 0 && freq >= 5120) {
107572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
108572ff6f6SMatthew Dillon ((freq - 4800) / 20 << 2), 8);
109572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(3, 2);
110572ff6f6SMatthew Dillon } else if ((freq % 10) == 0) {
111572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
112572ff6f6SMatthew Dillon ((freq - 4800) / 10 << 1), 8);
113572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(2, 2);
114572ff6f6SMatthew Dillon } else if ((freq % 5) == 0) {
115572ff6f6SMatthew Dillon channelSel = ath_hal_reverseBits(
116572ff6f6SMatthew Dillon (freq - 4800) / 5, 8);
117572ff6f6SMatthew Dillon aModeRefSel = ath_hal_reverseBits(1, 2);
118572ff6f6SMatthew Dillon } else {
119572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
120572ff6f6SMatthew Dillon __func__, freq);
121572ff6f6SMatthew Dillon return AH_FALSE;
122572ff6f6SMatthew Dillon }
123572ff6f6SMatthew Dillon
124572ff6f6SMatthew Dillon reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
125572ff6f6SMatthew Dillon (1 << 12) | 0x1;
126572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
127572ff6f6SMatthew Dillon
128572ff6f6SMatthew Dillon reg32 >>= 8;
129572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
130572ff6f6SMatthew Dillon
131572ff6f6SMatthew Dillon AH_PRIVATE(ah)->ah_curchan = chan;
132572ff6f6SMatthew Dillon return AH_TRUE;
133572ff6f6SMatthew Dillon }
134572ff6f6SMatthew Dillon
135572ff6f6SMatthew Dillon /*
136572ff6f6SMatthew Dillon * Reads EEPROM header info from device structure and programs
137572ff6f6SMatthew Dillon * all rf registers
138572ff6f6SMatthew Dillon *
139572ff6f6SMatthew Dillon * REQUIRES: Access to the analog rf device
140572ff6f6SMatthew Dillon */
141572ff6f6SMatthew Dillon static HAL_BOOL
ar2317SetRfRegs(struct ath_hal * ah,const struct ieee80211_channel * chan,uint16_t modesIndex,uint16_t * rfXpdGain)142572ff6f6SMatthew Dillon ar2317SetRfRegs(struct ath_hal *ah,
143572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
144572ff6f6SMatthew Dillon uint16_t modesIndex, uint16_t *rfXpdGain)
145572ff6f6SMatthew Dillon {
146572ff6f6SMatthew Dillon #define RF_BANK_SETUP(_priv, _ix, _col) do { \
147572ff6f6SMatthew Dillon int i; \
148572ff6f6SMatthew Dillon for (i = 0; i < N(ar5212Bank##_ix##_2317); i++) \
149572ff6f6SMatthew Dillon (_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2317[i][_col];\
150572ff6f6SMatthew Dillon } while (0)
151572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
152572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
153572ff6f6SMatthew Dillon uint16_t ob2GHz = 0, db2GHz = 0;
154572ff6f6SMatthew Dillon struct ar2317State *priv = AR2317(ah);
155572ff6f6SMatthew Dillon int regWrites = 0;
156572ff6f6SMatthew Dillon
157572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
158572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags, modesIndex);
159572ff6f6SMatthew Dillon
160572ff6f6SMatthew Dillon HALASSERT(priv);
161572ff6f6SMatthew Dillon
162572ff6f6SMatthew Dillon /* Setup rf parameters */
163572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_B(chan)) {
164572ff6f6SMatthew Dillon ob2GHz = ee->ee_obFor24;
165572ff6f6SMatthew Dillon db2GHz = ee->ee_dbFor24;
166572ff6f6SMatthew Dillon } else {
167572ff6f6SMatthew Dillon ob2GHz = ee->ee_obFor24g;
168572ff6f6SMatthew Dillon db2GHz = ee->ee_dbFor24g;
169572ff6f6SMatthew Dillon }
170572ff6f6SMatthew Dillon
171572ff6f6SMatthew Dillon /* Bank 1 Write */
172572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 1, 1);
173572ff6f6SMatthew Dillon
174572ff6f6SMatthew Dillon /* Bank 2 Write */
175572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 2, modesIndex);
176572ff6f6SMatthew Dillon
177572ff6f6SMatthew Dillon /* Bank 3 Write */
178572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 3, modesIndex);
179572ff6f6SMatthew Dillon
180572ff6f6SMatthew Dillon /* Bank 6 Write */
181572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 6, modesIndex);
182572ff6f6SMatthew Dillon
183572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 193, 0);
184572ff6f6SMatthew Dillon ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 190, 0);
185572ff6f6SMatthew Dillon
186572ff6f6SMatthew Dillon /* Bank 7 Setup */
187572ff6f6SMatthew Dillon RF_BANK_SETUP(priv, 7, modesIndex);
188572ff6f6SMatthew Dillon
189572ff6f6SMatthew Dillon /* Write Analog registers */
190572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank1_2317, priv->Bank1Data, regWrites);
191572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank2_2317, priv->Bank2Data, regWrites);
192572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank3_2317, priv->Bank3Data, regWrites);
193572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank6_2317, priv->Bank6Data, regWrites);
194572ff6f6SMatthew Dillon HAL_INI_WRITE_BANK(ah, ar5212Bank7_2317, priv->Bank7Data, regWrites);
195572ff6f6SMatthew Dillon /* Now that we have reprogrammed rfgain value, clear the flag. */
196572ff6f6SMatthew Dillon ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
197572ff6f6SMatthew Dillon
198572ff6f6SMatthew Dillon return AH_TRUE;
199572ff6f6SMatthew Dillon #undef RF_BANK_SETUP
200572ff6f6SMatthew Dillon }
201572ff6f6SMatthew Dillon
202572ff6f6SMatthew Dillon /*
203572ff6f6SMatthew Dillon * Return a reference to the requested RF Bank.
204572ff6f6SMatthew Dillon */
205572ff6f6SMatthew Dillon static uint32_t *
ar2317GetRfBank(struct ath_hal * ah,int bank)206572ff6f6SMatthew Dillon ar2317GetRfBank(struct ath_hal *ah, int bank)
207572ff6f6SMatthew Dillon {
208572ff6f6SMatthew Dillon struct ar2317State *priv = AR2317(ah);
209572ff6f6SMatthew Dillon
210572ff6f6SMatthew Dillon HALASSERT(priv != AH_NULL);
211572ff6f6SMatthew Dillon switch (bank) {
212572ff6f6SMatthew Dillon case 1: return priv->Bank1Data;
213572ff6f6SMatthew Dillon case 2: return priv->Bank2Data;
214572ff6f6SMatthew Dillon case 3: return priv->Bank3Data;
215572ff6f6SMatthew Dillon case 6: return priv->Bank6Data;
216572ff6f6SMatthew Dillon case 7: return priv->Bank7Data;
217572ff6f6SMatthew Dillon }
218572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
219572ff6f6SMatthew Dillon __func__, bank);
220572ff6f6SMatthew Dillon return AH_NULL;
221572ff6f6SMatthew Dillon }
222572ff6f6SMatthew Dillon
223572ff6f6SMatthew Dillon /*
224572ff6f6SMatthew Dillon * Return indices surrounding the value in sorted integer lists.
225572ff6f6SMatthew Dillon *
226572ff6f6SMatthew Dillon * NB: the input list is assumed to be sorted in ascending order
227572ff6f6SMatthew Dillon */
228572ff6f6SMatthew Dillon static void
GetLowerUpperIndex(int16_t v,const uint16_t * lp,uint16_t listSize,uint32_t * vlo,uint32_t * vhi)229572ff6f6SMatthew Dillon GetLowerUpperIndex(int16_t v, const uint16_t *lp, uint16_t listSize,
230572ff6f6SMatthew Dillon uint32_t *vlo, uint32_t *vhi)
231572ff6f6SMatthew Dillon {
232572ff6f6SMatthew Dillon int16_t target = v;
233572ff6f6SMatthew Dillon const int16_t *ep = lp+listSize;
234572ff6f6SMatthew Dillon const int16_t *tp;
235572ff6f6SMatthew Dillon
236572ff6f6SMatthew Dillon /*
237572ff6f6SMatthew Dillon * Check first and last elements for out-of-bounds conditions.
238572ff6f6SMatthew Dillon */
239572ff6f6SMatthew Dillon if (target < lp[0]) {
240572ff6f6SMatthew Dillon *vlo = *vhi = 0;
241572ff6f6SMatthew Dillon return;
242572ff6f6SMatthew Dillon }
243572ff6f6SMatthew Dillon if (target >= ep[-1]) {
244572ff6f6SMatthew Dillon *vlo = *vhi = listSize - 1;
245572ff6f6SMatthew Dillon return;
246572ff6f6SMatthew Dillon }
247572ff6f6SMatthew Dillon
248572ff6f6SMatthew Dillon /* look for value being near or between 2 values in list */
249572ff6f6SMatthew Dillon for (tp = lp; tp < ep; tp++) {
250572ff6f6SMatthew Dillon /*
251572ff6f6SMatthew Dillon * If value is close to the current value of the list
252572ff6f6SMatthew Dillon * then target is not between values, it is one of the values
253572ff6f6SMatthew Dillon */
254572ff6f6SMatthew Dillon if (*tp == target) {
255572ff6f6SMatthew Dillon *vlo = *vhi = tp - (const int16_t *) lp;
256572ff6f6SMatthew Dillon return;
257572ff6f6SMatthew Dillon }
258572ff6f6SMatthew Dillon /*
259572ff6f6SMatthew Dillon * Look for value being between current value and next value
260572ff6f6SMatthew Dillon * if so return these 2 values
261572ff6f6SMatthew Dillon */
262572ff6f6SMatthew Dillon if (target < tp[1]) {
263572ff6f6SMatthew Dillon *vlo = tp - (const int16_t *) lp;
264572ff6f6SMatthew Dillon *vhi = *vlo + 1;
265572ff6f6SMatthew Dillon return;
266572ff6f6SMatthew Dillon }
267572ff6f6SMatthew Dillon }
268572ff6f6SMatthew Dillon }
269572ff6f6SMatthew Dillon
270572ff6f6SMatthew Dillon /*
271572ff6f6SMatthew Dillon * Fill the Vpdlist for indices Pmax-Pmin
272572ff6f6SMatthew Dillon */
273572ff6f6SMatthew Dillon static HAL_BOOL
ar2317FillVpdTable(uint32_t pdGainIdx,int16_t Pmin,int16_t Pmax,const int16_t * pwrList,const int16_t * VpdList,uint16_t numIntercepts,uint16_t retVpdList[][64])274572ff6f6SMatthew Dillon ar2317FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t Pmax,
275572ff6f6SMatthew Dillon const int16_t *pwrList, const int16_t *VpdList,
276572ff6f6SMatthew Dillon uint16_t numIntercepts, uint16_t retVpdList[][64])
277572ff6f6SMatthew Dillon {
278572ff6f6SMatthew Dillon uint16_t ii, jj, kk;
279572ff6f6SMatthew Dillon int16_t currPwr = (int16_t)(2*Pmin);
280572ff6f6SMatthew Dillon /* since Pmin is pwr*2 and pwrList is 4*pwr */
281572ff6f6SMatthew Dillon uint32_t idxL, idxR;
282572ff6f6SMatthew Dillon
283572ff6f6SMatthew Dillon ii = 0;
284572ff6f6SMatthew Dillon jj = 0;
285572ff6f6SMatthew Dillon
286572ff6f6SMatthew Dillon if (numIntercepts < 2)
287572ff6f6SMatthew Dillon return AH_FALSE;
288572ff6f6SMatthew Dillon
289572ff6f6SMatthew Dillon while (ii <= (uint16_t)(Pmax - Pmin)) {
290572ff6f6SMatthew Dillon GetLowerUpperIndex(currPwr, pwrList, numIntercepts,
291572ff6f6SMatthew Dillon &(idxL), &(idxR));
292572ff6f6SMatthew Dillon if (idxR < 1)
293572ff6f6SMatthew Dillon idxR = 1; /* extrapolate below */
294572ff6f6SMatthew Dillon if (idxL == (uint32_t)(numIntercepts - 1))
295572ff6f6SMatthew Dillon idxL = numIntercepts - 2; /* extrapolate above */
296572ff6f6SMatthew Dillon if (pwrList[idxL] == pwrList[idxR])
297572ff6f6SMatthew Dillon kk = VpdList[idxL];
298572ff6f6SMatthew Dillon else
299572ff6f6SMatthew Dillon kk = (uint16_t)
300572ff6f6SMatthew Dillon (((currPwr - pwrList[idxL])*VpdList[idxR]+
301572ff6f6SMatthew Dillon (pwrList[idxR] - currPwr)*VpdList[idxL])/
302572ff6f6SMatthew Dillon (pwrList[idxR] - pwrList[idxL]));
303572ff6f6SMatthew Dillon retVpdList[pdGainIdx][ii] = kk;
304572ff6f6SMatthew Dillon ii++;
305572ff6f6SMatthew Dillon currPwr += 2; /* half dB steps */
306572ff6f6SMatthew Dillon }
307572ff6f6SMatthew Dillon
308572ff6f6SMatthew Dillon return AH_TRUE;
309572ff6f6SMatthew Dillon }
310572ff6f6SMatthew Dillon
311572ff6f6SMatthew Dillon /*
312572ff6f6SMatthew Dillon * Returns interpolated or the scaled up interpolated value
313572ff6f6SMatthew Dillon */
314572ff6f6SMatthew Dillon static int16_t
interpolate_signed(uint16_t target,uint16_t srcLeft,uint16_t srcRight,int16_t targetLeft,int16_t targetRight)315572ff6f6SMatthew Dillon interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
316572ff6f6SMatthew Dillon int16_t targetLeft, int16_t targetRight)
317572ff6f6SMatthew Dillon {
318572ff6f6SMatthew Dillon int16_t rv;
319572ff6f6SMatthew Dillon
320572ff6f6SMatthew Dillon if (srcRight != srcLeft) {
321572ff6f6SMatthew Dillon rv = ((target - srcLeft)*targetRight +
322572ff6f6SMatthew Dillon (srcRight - target)*targetLeft) / (srcRight - srcLeft);
323572ff6f6SMatthew Dillon } else {
324572ff6f6SMatthew Dillon rv = targetLeft;
325572ff6f6SMatthew Dillon }
326572ff6f6SMatthew Dillon return rv;
327572ff6f6SMatthew Dillon }
328572ff6f6SMatthew Dillon
329572ff6f6SMatthew Dillon /*
330572ff6f6SMatthew Dillon * Uses the data points read from EEPROM to reconstruct the pdadc power table
331572ff6f6SMatthew Dillon * Called by ar2317SetPowerTable()
332572ff6f6SMatthew Dillon */
333572ff6f6SMatthew Dillon static int
ar2317getGainBoundariesAndPdadcsForPowers(struct ath_hal * ah,uint16_t channel,const RAW_DATA_STRUCT_2317 * pRawDataset,uint16_t pdGainOverlap_t2,int16_t * pMinCalPower,uint16_t pPdGainBoundaries[],uint16_t pPdGainValues[],uint16_t pPDADCValues[])334572ff6f6SMatthew Dillon ar2317getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
335572ff6f6SMatthew Dillon const RAW_DATA_STRUCT_2317 *pRawDataset,
336572ff6f6SMatthew Dillon uint16_t pdGainOverlap_t2,
337572ff6f6SMatthew Dillon int16_t *pMinCalPower, uint16_t pPdGainBoundaries[],
338572ff6f6SMatthew Dillon uint16_t pPdGainValues[], uint16_t pPDADCValues[])
339572ff6f6SMatthew Dillon {
340572ff6f6SMatthew Dillon struct ar2317State *priv = AR2317(ah);
341572ff6f6SMatthew Dillon #define VpdTable_L priv->vpdTable_L
342572ff6f6SMatthew Dillon #define VpdTable_R priv->vpdTable_R
343572ff6f6SMatthew Dillon #define VpdTable_I priv->vpdTable_I
344572ff6f6SMatthew Dillon /* XXX excessive stack usage? */
345572ff6f6SMatthew Dillon uint32_t ii, jj, kk;
346572ff6f6SMatthew Dillon int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
347572ff6f6SMatthew Dillon uint32_t idxL, idxR;
348572ff6f6SMatthew Dillon uint32_t numPdGainsUsed = 0;
349572ff6f6SMatthew Dillon /*
350572ff6f6SMatthew Dillon * If desired to support -ve power levels in future, just
351572ff6f6SMatthew Dillon * change pwr_I_0 to signed 5-bits.
352572ff6f6SMatthew Dillon */
353572ff6f6SMatthew Dillon int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
354*b14ca477SMatthew Dillon /* to accommodate -ve power levels later on. */
355572ff6f6SMatthew Dillon int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
356*b14ca477SMatthew Dillon /* to accommodate -ve power levels later on */
357572ff6f6SMatthew Dillon uint16_t numVpd = 0;
358572ff6f6SMatthew Dillon uint16_t Vpd_step;
359572ff6f6SMatthew Dillon int16_t tmpVal ;
360572ff6f6SMatthew Dillon uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
361572ff6f6SMatthew Dillon
362572ff6f6SMatthew Dillon /* Get upper lower index */
363572ff6f6SMatthew Dillon GetLowerUpperIndex(channel, pRawDataset->pChannels,
364572ff6f6SMatthew Dillon pRawDataset->numChannels, &(idxL), &(idxR));
365572ff6f6SMatthew Dillon
366572ff6f6SMatthew Dillon for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
367572ff6f6SMatthew Dillon jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
368572ff6f6SMatthew Dillon /* work backwards 'cause highest pdGain for lowest power */
369572ff6f6SMatthew Dillon numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
370572ff6f6SMatthew Dillon if (numVpd > 0) {
371572ff6f6SMatthew Dillon pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
372572ff6f6SMatthew Dillon Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
373572ff6f6SMatthew Dillon if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
374572ff6f6SMatthew Dillon Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
375572ff6f6SMatthew Dillon }
376572ff6f6SMatthew Dillon Pmin_t2[numPdGainsUsed] = (int16_t)
377572ff6f6SMatthew Dillon (Pmin_t2[numPdGainsUsed] / 2);
378572ff6f6SMatthew Dillon Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
379572ff6f6SMatthew Dillon if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
380572ff6f6SMatthew Dillon Pmax_t2[numPdGainsUsed] =
381572ff6f6SMatthew Dillon pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
382572ff6f6SMatthew Dillon Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
383572ff6f6SMatthew Dillon ar2317FillVpdTable(
384572ff6f6SMatthew Dillon numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed],
385572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]),
386572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
387572ff6f6SMatthew Dillon );
388572ff6f6SMatthew Dillon ar2317FillVpdTable(
389572ff6f6SMatthew Dillon numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed],
390572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
391572ff6f6SMatthew Dillon &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
392572ff6f6SMatthew Dillon );
393572ff6f6SMatthew Dillon for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
394572ff6f6SMatthew Dillon VpdTable_I[numPdGainsUsed][kk] =
395572ff6f6SMatthew Dillon interpolate_signed(
396572ff6f6SMatthew Dillon channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
397572ff6f6SMatthew Dillon (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
398572ff6f6SMatthew Dillon }
399572ff6f6SMatthew Dillon /* fill VpdTable_I for this pdGain */
400572ff6f6SMatthew Dillon numPdGainsUsed++;
401572ff6f6SMatthew Dillon }
402572ff6f6SMatthew Dillon /* if this pdGain is used */
403572ff6f6SMatthew Dillon }
404572ff6f6SMatthew Dillon
405572ff6f6SMatthew Dillon *pMinCalPower = Pmin_t2[0];
406572ff6f6SMatthew Dillon kk = 0; /* index for the final table */
407572ff6f6SMatthew Dillon for (ii = 0; ii < numPdGainsUsed; ii++) {
408572ff6f6SMatthew Dillon if (ii == (numPdGainsUsed - 1))
409572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = Pmax_t2[ii] +
410572ff6f6SMatthew Dillon PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
411572ff6f6SMatthew Dillon else
412572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = (uint16_t)
413572ff6f6SMatthew Dillon ((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
414572ff6f6SMatthew Dillon if (pPdGainBoundaries[ii] > 63) {
415572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
416572ff6f6SMatthew Dillon "%s: clamp pPdGainBoundaries[%d] %d\n",
417572ff6f6SMatthew Dillon __func__, ii, pPdGainBoundaries[ii]);/*XXX*/
418572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = 63;
419572ff6f6SMatthew Dillon }
420572ff6f6SMatthew Dillon
421572ff6f6SMatthew Dillon /* Find starting index for this pdGain */
422572ff6f6SMatthew Dillon if (ii == 0)
423572ff6f6SMatthew Dillon ss = 0; /* for the first pdGain, start from index 0 */
424572ff6f6SMatthew Dillon else
425572ff6f6SMatthew Dillon ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) -
426572ff6f6SMatthew Dillon pdGainOverlap_t2;
427572ff6f6SMatthew Dillon Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
428572ff6f6SMatthew Dillon Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
429572ff6f6SMatthew Dillon /*
430572ff6f6SMatthew Dillon *-ve ss indicates need to extrapolate data below for this pdGain
431572ff6f6SMatthew Dillon */
432572ff6f6SMatthew Dillon while (ss < 0) {
433572ff6f6SMatthew Dillon tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
434572ff6f6SMatthew Dillon pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
435572ff6f6SMatthew Dillon ss++;
436572ff6f6SMatthew Dillon }
437572ff6f6SMatthew Dillon
438572ff6f6SMatthew Dillon sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
439572ff6f6SMatthew Dillon tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
440572ff6f6SMatthew Dillon maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
441572ff6f6SMatthew Dillon
442572ff6f6SMatthew Dillon while (ss < (int16_t)maxIndex)
443572ff6f6SMatthew Dillon pPDADCValues[kk++] = VpdTable_I[ii][ss++];
444572ff6f6SMatthew Dillon
445572ff6f6SMatthew Dillon Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
446572ff6f6SMatthew Dillon VpdTable_I[ii][sizeCurrVpdTable-2]);
447572ff6f6SMatthew Dillon Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
448572ff6f6SMatthew Dillon /*
449572ff6f6SMatthew Dillon * for last gain, pdGainBoundary == Pmax_t2, so will
450572ff6f6SMatthew Dillon * have to extrapolate
451572ff6f6SMatthew Dillon */
452572ff6f6SMatthew Dillon if (tgtIndex > maxIndex) { /* need to extrapolate above */
453572ff6f6SMatthew Dillon while(ss < (int16_t)tgtIndex) {
454572ff6f6SMatthew Dillon tmpVal = (uint16_t)
455572ff6f6SMatthew Dillon (VpdTable_I[ii][sizeCurrVpdTable-1] +
456572ff6f6SMatthew Dillon (ss-maxIndex)*Vpd_step);
457572ff6f6SMatthew Dillon pPDADCValues[kk++] = (tmpVal > 127) ?
458572ff6f6SMatthew Dillon 127 : tmpVal;
459572ff6f6SMatthew Dillon ss++;
460572ff6f6SMatthew Dillon }
461572ff6f6SMatthew Dillon } /* extrapolated above */
462572ff6f6SMatthew Dillon } /* for all pdGainUsed */
463572ff6f6SMatthew Dillon
464572ff6f6SMatthew Dillon while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
465572ff6f6SMatthew Dillon pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
466572ff6f6SMatthew Dillon ii++;
467572ff6f6SMatthew Dillon }
468572ff6f6SMatthew Dillon while (kk < 128) {
469572ff6f6SMatthew Dillon pPDADCValues[kk] = pPDADCValues[kk-1];
470572ff6f6SMatthew Dillon kk++;
471572ff6f6SMatthew Dillon }
472572ff6f6SMatthew Dillon
473572ff6f6SMatthew Dillon return numPdGainsUsed;
474572ff6f6SMatthew Dillon #undef VpdTable_L
475572ff6f6SMatthew Dillon #undef VpdTable_R
476572ff6f6SMatthew Dillon #undef VpdTable_I
477572ff6f6SMatthew Dillon }
478572ff6f6SMatthew Dillon
479572ff6f6SMatthew Dillon static HAL_BOOL
ar2317SetPowerTable(struct ath_hal * ah,int16_t * minPower,int16_t * maxPower,const struct ieee80211_channel * chan,uint16_t * rfXpdGain)480572ff6f6SMatthew Dillon ar2317SetPowerTable(struct ath_hal *ah,
481572ff6f6SMatthew Dillon int16_t *minPower, int16_t *maxPower,
482572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
483572ff6f6SMatthew Dillon uint16_t *rfXpdGain)
484572ff6f6SMatthew Dillon {
485572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
486572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
487572ff6f6SMatthew Dillon const RAW_DATA_STRUCT_2317 *pRawDataset = AH_NULL;
488572ff6f6SMatthew Dillon uint16_t pdGainOverlap_t2;
489572ff6f6SMatthew Dillon int16_t minCalPower2317_t2;
490572ff6f6SMatthew Dillon uint16_t *pdadcValues = ahp->ah_pcdacTable;
491572ff6f6SMatthew Dillon uint16_t gainBoundaries[4];
492572ff6f6SMatthew Dillon uint32_t reg32, regoffset;
493572ff6f6SMatthew Dillon int i, numPdGainsUsed;
494572ff6f6SMatthew Dillon #ifndef AH_USE_INIPDGAIN
495572ff6f6SMatthew Dillon uint32_t tpcrg1;
496572ff6f6SMatthew Dillon #endif
497572ff6f6SMatthew Dillon
498572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
499572ff6f6SMatthew Dillon __func__, chan->ic_freq, chan->ic_flags);
500572ff6f6SMatthew Dillon
501572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
502572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
503572ff6f6SMatthew Dillon else if (IEEE80211_IS_CHAN_B(chan))
504572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
505572ff6f6SMatthew Dillon else {
506572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
507572ff6f6SMatthew Dillon return AH_FALSE;
508572ff6f6SMatthew Dillon }
509572ff6f6SMatthew Dillon
510572ff6f6SMatthew Dillon pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
511572ff6f6SMatthew Dillon AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
512572ff6f6SMatthew Dillon
513572ff6f6SMatthew Dillon numPdGainsUsed = ar2317getGainBoundariesAndPdadcsForPowers(ah,
514572ff6f6SMatthew Dillon chan->channel, pRawDataset, pdGainOverlap_t2,
515572ff6f6SMatthew Dillon &minCalPower2317_t2,gainBoundaries, rfXpdGain, pdadcValues);
516572ff6f6SMatthew Dillon HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
517572ff6f6SMatthew Dillon
518572ff6f6SMatthew Dillon #ifdef AH_USE_INIPDGAIN
519572ff6f6SMatthew Dillon /*
520572ff6f6SMatthew Dillon * Use pd_gains curve from eeprom; Atheros always uses
521572ff6f6SMatthew Dillon * the default curve from the ini file but some vendors
522572ff6f6SMatthew Dillon * (e.g. Zcomax) want to override this curve and not
523572ff6f6SMatthew Dillon * honoring their settings results in tx power 5dBm low.
524572ff6f6SMatthew Dillon */
525572ff6f6SMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
526572ff6f6SMatthew Dillon (pRawDataset->pDataPerChannel[0].numPdGains - 1));
527572ff6f6SMatthew Dillon #else
528572ff6f6SMatthew Dillon tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);
529572ff6f6SMatthew Dillon tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)
530572ff6f6SMatthew Dillon | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
531572ff6f6SMatthew Dillon switch (numPdGainsUsed) {
532572ff6f6SMatthew Dillon case 3:
533572ff6f6SMatthew Dillon tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;
534572ff6f6SMatthew Dillon tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
535572ff6f6SMatthew Dillon /* fall thru... */
536572ff6f6SMatthew Dillon case 2:
537572ff6f6SMatthew Dillon tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;
538572ff6f6SMatthew Dillon tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
539572ff6f6SMatthew Dillon /* fall thru... */
540572ff6f6SMatthew Dillon case 1:
541572ff6f6SMatthew Dillon tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;
542572ff6f6SMatthew Dillon tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
543572ff6f6SMatthew Dillon break;
544572ff6f6SMatthew Dillon }
545572ff6f6SMatthew Dillon #ifdef AH_DEBUG
546572ff6f6SMatthew Dillon if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))
547572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "
548572ff6f6SMatthew Dillon "pd_gains (default 0x%x, calculated 0x%x)\n",
549572ff6f6SMatthew Dillon __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);
550572ff6f6SMatthew Dillon #endif
551572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);
552572ff6f6SMatthew Dillon #endif
553572ff6f6SMatthew Dillon
554572ff6f6SMatthew Dillon /*
555572ff6f6SMatthew Dillon * Note the pdadc table may not start at 0 dBm power, could be
556572ff6f6SMatthew Dillon * negative or greater than 0. Need to offset the power
557572ff6f6SMatthew Dillon * values by the amount of minPower for griffin
558572ff6f6SMatthew Dillon */
559572ff6f6SMatthew Dillon if (minCalPower2317_t2 != 0)
560572ff6f6SMatthew Dillon ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2317_t2);
561572ff6f6SMatthew Dillon else
562572ff6f6SMatthew Dillon ahp->ah_txPowerIndexOffset = 0;
563572ff6f6SMatthew Dillon
564572ff6f6SMatthew Dillon /* Finally, write the power values into the baseband power table */
565572ff6f6SMatthew Dillon regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
566572ff6f6SMatthew Dillon for (i = 0; i < 32; i++) {
567572ff6f6SMatthew Dillon reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0) |
568572ff6f6SMatthew Dillon ((pdadcValues[4*i + 1] & 0xFF) << 8) |
569572ff6f6SMatthew Dillon ((pdadcValues[4*i + 2] & 0xFF) << 16) |
570572ff6f6SMatthew Dillon ((pdadcValues[4*i + 3] & 0xFF) << 24) ;
571572ff6f6SMatthew Dillon OS_REG_WRITE(ah, regoffset, reg32);
572572ff6f6SMatthew Dillon regoffset += 4;
573572ff6f6SMatthew Dillon }
574572ff6f6SMatthew Dillon
575572ff6f6SMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TPCRG5,
576572ff6f6SMatthew Dillon SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
577572ff6f6SMatthew Dillon SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
578572ff6f6SMatthew Dillon SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
579572ff6f6SMatthew Dillon SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
580572ff6f6SMatthew Dillon SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
581572ff6f6SMatthew Dillon
582572ff6f6SMatthew Dillon return AH_TRUE;
583572ff6f6SMatthew Dillon }
584572ff6f6SMatthew Dillon
585572ff6f6SMatthew Dillon static int16_t
ar2317GetMinPower(struct ath_hal * ah,const RAW_DATA_PER_CHANNEL_2317 * data)586572ff6f6SMatthew Dillon ar2317GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data)
587572ff6f6SMatthew Dillon {
588572ff6f6SMatthew Dillon uint32_t ii,jj;
589572ff6f6SMatthew Dillon uint16_t Pmin=0,numVpd;
590572ff6f6SMatthew Dillon
591572ff6f6SMatthew Dillon for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
592572ff6f6SMatthew Dillon jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
593572ff6f6SMatthew Dillon /* work backwards 'cause highest pdGain for lowest power */
594572ff6f6SMatthew Dillon numVpd = data->pDataPerPDGain[jj].numVpd;
595572ff6f6SMatthew Dillon if (numVpd > 0) {
596572ff6f6SMatthew Dillon Pmin = data->pDataPerPDGain[jj].pwr_t4[0];
597572ff6f6SMatthew Dillon return(Pmin);
598572ff6f6SMatthew Dillon }
599572ff6f6SMatthew Dillon }
600572ff6f6SMatthew Dillon return(Pmin);
601572ff6f6SMatthew Dillon }
602572ff6f6SMatthew Dillon
603572ff6f6SMatthew Dillon static int16_t
ar2317GetMaxPower(struct ath_hal * ah,const RAW_DATA_PER_CHANNEL_2317 * data)604572ff6f6SMatthew Dillon ar2317GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data)
605572ff6f6SMatthew Dillon {
606572ff6f6SMatthew Dillon uint32_t ii;
607572ff6f6SMatthew Dillon uint16_t Pmax=0,numVpd;
608572ff6f6SMatthew Dillon uint16_t vpdmax;
609572ff6f6SMatthew Dillon
610572ff6f6SMatthew Dillon for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
611572ff6f6SMatthew Dillon /* work forwards cuase lowest pdGain for highest power */
612572ff6f6SMatthew Dillon numVpd = data->pDataPerPDGain[ii].numVpd;
613572ff6f6SMatthew Dillon if (numVpd > 0) {
614572ff6f6SMatthew Dillon Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
615572ff6f6SMatthew Dillon vpdmax = data->pDataPerPDGain[ii].Vpd[numVpd-1];
616572ff6f6SMatthew Dillon return(Pmax);
617572ff6f6SMatthew Dillon }
618572ff6f6SMatthew Dillon }
619572ff6f6SMatthew Dillon return(Pmax);
620572ff6f6SMatthew Dillon }
621572ff6f6SMatthew Dillon
622572ff6f6SMatthew Dillon static HAL_BOOL
ar2317GetChannelMaxMinPower(struct ath_hal * ah,const struct ieee80211_channel * chan,int16_t * maxPow,int16_t * minPow)623572ff6f6SMatthew Dillon ar2317GetChannelMaxMinPower(struct ath_hal *ah,
624572ff6f6SMatthew Dillon const struct ieee80211_channel *chan,
625572ff6f6SMatthew Dillon int16_t *maxPow, int16_t *minPow)
626572ff6f6SMatthew Dillon {
627572ff6f6SMatthew Dillon uint16_t freq = chan->ic_freq; /* NB: never mapped */
628572ff6f6SMatthew Dillon const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
629572ff6f6SMatthew Dillon const RAW_DATA_STRUCT_2317 *pRawDataset = AH_NULL;
630572ff6f6SMatthew Dillon const RAW_DATA_PER_CHANNEL_2317 *data=AH_NULL;
631572ff6f6SMatthew Dillon uint16_t numChannels;
632572ff6f6SMatthew Dillon int totalD,totalF, totalMin,last, i;
633572ff6f6SMatthew Dillon
634572ff6f6SMatthew Dillon *maxPow = 0;
635572ff6f6SMatthew Dillon
636572ff6f6SMatthew Dillon if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
637572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
638572ff6f6SMatthew Dillon else if (IEEE80211_IS_CHAN_B(chan))
639572ff6f6SMatthew Dillon pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
640572ff6f6SMatthew Dillon else
641572ff6f6SMatthew Dillon return(AH_FALSE);
642572ff6f6SMatthew Dillon
643572ff6f6SMatthew Dillon numChannels = pRawDataset->numChannels;
644572ff6f6SMatthew Dillon data = pRawDataset->pDataPerChannel;
645572ff6f6SMatthew Dillon
646572ff6f6SMatthew Dillon /* Make sure the channel is in the range of the TP values
647572ff6f6SMatthew Dillon * (freq piers)
648572ff6f6SMatthew Dillon */
649572ff6f6SMatthew Dillon if (numChannels < 1)
650572ff6f6SMatthew Dillon return(AH_FALSE);
651572ff6f6SMatthew Dillon
652572ff6f6SMatthew Dillon if ((freq < data[0].channelValue) ||
653572ff6f6SMatthew Dillon (freq > data[numChannels-1].channelValue)) {
654572ff6f6SMatthew Dillon if (freq < data[0].channelValue) {
655572ff6f6SMatthew Dillon *maxPow = ar2317GetMaxPower(ah, &data[0]);
656572ff6f6SMatthew Dillon *minPow = ar2317GetMinPower(ah, &data[0]);
657572ff6f6SMatthew Dillon return(AH_TRUE);
658572ff6f6SMatthew Dillon } else {
659572ff6f6SMatthew Dillon *maxPow = ar2317GetMaxPower(ah, &data[numChannels - 1]);
660572ff6f6SMatthew Dillon *minPow = ar2317GetMinPower(ah, &data[numChannels - 1]);
661572ff6f6SMatthew Dillon return(AH_TRUE);
662572ff6f6SMatthew Dillon }
663572ff6f6SMatthew Dillon }
664572ff6f6SMatthew Dillon
665572ff6f6SMatthew Dillon /* Linearly interpolate the power value now */
666572ff6f6SMatthew Dillon for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
667572ff6f6SMatthew Dillon last = i++);
668572ff6f6SMatthew Dillon totalD = data[i].channelValue - data[last].channelValue;
669572ff6f6SMatthew Dillon if (totalD > 0) {
670572ff6f6SMatthew Dillon totalF = ar2317GetMaxPower(ah, &data[i]) - ar2317GetMaxPower(ah, &data[last]);
671572ff6f6SMatthew Dillon *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
672572ff6f6SMatthew Dillon ar2317GetMaxPower(ah, &data[last])*totalD)/totalD);
673572ff6f6SMatthew Dillon totalMin = ar2317GetMinPower(ah, &data[i]) - ar2317GetMinPower(ah, &data[last]);
674572ff6f6SMatthew Dillon *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
675572ff6f6SMatthew Dillon ar2317GetMinPower(ah, &data[last])*totalD)/totalD);
676572ff6f6SMatthew Dillon return(AH_TRUE);
677572ff6f6SMatthew Dillon } else {
678572ff6f6SMatthew Dillon if (freq == data[i].channelValue) {
679572ff6f6SMatthew Dillon *maxPow = ar2317GetMaxPower(ah, &data[i]);
680572ff6f6SMatthew Dillon *minPow = ar2317GetMinPower(ah, &data[i]);
681572ff6f6SMatthew Dillon return(AH_TRUE);
682572ff6f6SMatthew Dillon } else
683572ff6f6SMatthew Dillon return(AH_FALSE);
684572ff6f6SMatthew Dillon }
685572ff6f6SMatthew Dillon }
686572ff6f6SMatthew Dillon
687572ff6f6SMatthew Dillon /*
688572ff6f6SMatthew Dillon * Free memory for analog bank scratch buffers
689572ff6f6SMatthew Dillon */
690572ff6f6SMatthew Dillon static void
ar2317RfDetach(struct ath_hal * ah)691572ff6f6SMatthew Dillon ar2317RfDetach(struct ath_hal *ah)
692572ff6f6SMatthew Dillon {
693572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
694572ff6f6SMatthew Dillon
695572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal != AH_NULL);
696572ff6f6SMatthew Dillon ath_hal_free(ahp->ah_rfHal);
697572ff6f6SMatthew Dillon ahp->ah_rfHal = AH_NULL;
698572ff6f6SMatthew Dillon }
699572ff6f6SMatthew Dillon
700572ff6f6SMatthew Dillon /*
701572ff6f6SMatthew Dillon * Allocate memory for analog bank scratch buffers
702572ff6f6SMatthew Dillon * Scratch Buffer will be reinitialized every reset so no need to zero now
703572ff6f6SMatthew Dillon */
704572ff6f6SMatthew Dillon static HAL_BOOL
ar2317RfAttach(struct ath_hal * ah,HAL_STATUS * status)705572ff6f6SMatthew Dillon ar2317RfAttach(struct ath_hal *ah, HAL_STATUS *status)
706572ff6f6SMatthew Dillon {
707572ff6f6SMatthew Dillon struct ath_hal_5212 *ahp = AH5212(ah);
708572ff6f6SMatthew Dillon struct ar2317State *priv;
709572ff6f6SMatthew Dillon
710572ff6f6SMatthew Dillon HALASSERT(ah->ah_magic == AR5212_MAGIC);
711572ff6f6SMatthew Dillon
712572ff6f6SMatthew Dillon HALASSERT(ahp->ah_rfHal == AH_NULL);
713572ff6f6SMatthew Dillon priv = ath_hal_malloc(sizeof(struct ar2317State));
714572ff6f6SMatthew Dillon if (priv == AH_NULL) {
715572ff6f6SMatthew Dillon HALDEBUG(ah, HAL_DEBUG_ANY,
716572ff6f6SMatthew Dillon "%s: cannot allocate private state\n", __func__);
717572ff6f6SMatthew Dillon *status = HAL_ENOMEM; /* XXX */
718572ff6f6SMatthew Dillon return AH_FALSE;
719572ff6f6SMatthew Dillon }
720572ff6f6SMatthew Dillon priv->base.rfDetach = ar2317RfDetach;
721572ff6f6SMatthew Dillon priv->base.writeRegs = ar2317WriteRegs;
722572ff6f6SMatthew Dillon priv->base.getRfBank = ar2317GetRfBank;
723572ff6f6SMatthew Dillon priv->base.setChannel = ar2317SetChannel;
724572ff6f6SMatthew Dillon priv->base.setRfRegs = ar2317SetRfRegs;
725572ff6f6SMatthew Dillon priv->base.setPowerTable = ar2317SetPowerTable;
726572ff6f6SMatthew Dillon priv->base.getChannelMaxMinPower = ar2317GetChannelMaxMinPower;
727572ff6f6SMatthew Dillon priv->base.getNfAdjust = ar5212GetNfAdjust;
728572ff6f6SMatthew Dillon
729572ff6f6SMatthew Dillon ahp->ah_pcdacTable = priv->pcdacTable;
730572ff6f6SMatthew Dillon ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
731572ff6f6SMatthew Dillon ahp->ah_rfHal = &priv->base;
732572ff6f6SMatthew Dillon
733572ff6f6SMatthew Dillon return AH_TRUE;
734572ff6f6SMatthew Dillon }
735572ff6f6SMatthew Dillon
736572ff6f6SMatthew Dillon static HAL_BOOL
ar2317Probe(struct ath_hal * ah)737572ff6f6SMatthew Dillon ar2317Probe(struct ath_hal *ah)
738572ff6f6SMatthew Dillon {
739572ff6f6SMatthew Dillon return IS_2317(ah);
740572ff6f6SMatthew Dillon }
741572ff6f6SMatthew Dillon AH_RF(RF2317, ar2317Probe, ar2317RfAttach);
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