Searched refs:LEVEL0_MPLL_FB_DIV_MASK (Results 1 – 2 of 2) sorted by relevance
/dflybsd-src/sys/dev/drm/radeon/ | ||
H A D | rv6xxd.h | 82 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8) macro |
H A D | rv6xx_dpm.c | 391 ~LEVEL0_MPLL_FB_DIV_MASK); in rv6xx_memory_clock_entry_set_feedback_divider() |