1*57e252bfSMichael Neumann /* 2*57e252bfSMichael Neumann * Copyright 2011 Advanced Micro Devices, Inc. 3*57e252bfSMichael Neumann * 4*57e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 5*57e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 6*57e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 7*57e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*57e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 9*57e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 10*57e252bfSMichael Neumann * 11*57e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 12*57e252bfSMichael Neumann * all copies or substantial portions of the Software. 13*57e252bfSMichael Neumann * 14*57e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*57e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*57e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*57e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*57e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*57e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*57e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 21*57e252bfSMichael Neumann * 22*57e252bfSMichael Neumann */ 23*57e252bfSMichael Neumann #ifndef RV6XXD_H 24*57e252bfSMichael Neumann #define RV6XXD_H 25*57e252bfSMichael Neumann 26*57e252bfSMichael Neumann /* RV6xx power management */ 27*57e252bfSMichael Neumann #define SPLL_CNTL_MODE 0x60c 28*57e252bfSMichael Neumann # define SPLL_DIV_SYNC (1 << 5) 29*57e252bfSMichael Neumann 30*57e252bfSMichael Neumann #define GENERAL_PWRMGT 0x618 31*57e252bfSMichael Neumann # define GLOBAL_PWRMGT_EN (1 << 0) 32*57e252bfSMichael Neumann # define STATIC_PM_EN (1 << 1) 33*57e252bfSMichael Neumann # define MOBILE_SU (1 << 2) 34*57e252bfSMichael Neumann # define THERMAL_PROTECTION_DIS (1 << 3) 35*57e252bfSMichael Neumann # define THERMAL_PROTECTION_TYPE (1 << 4) 36*57e252bfSMichael Neumann # define ENABLE_GEN2PCIE (1 << 5) 37*57e252bfSMichael Neumann # define SW_GPIO_INDEX(x) ((x) << 6) 38*57e252bfSMichael Neumann # define SW_GPIO_INDEX_MASK (3 << 6) 39*57e252bfSMichael Neumann # define LOW_VOLT_D2_ACPI (1 << 8) 40*57e252bfSMichael Neumann # define LOW_VOLT_D3_ACPI (1 << 9) 41*57e252bfSMichael Neumann # define VOLT_PWRMGT_EN (1 << 10) 42*57e252bfSMichael Neumann # define BACKBIAS_PAD_EN (1 << 16) 43*57e252bfSMichael Neumann # define BACKBIAS_VALUE (1 << 17) 44*57e252bfSMichael Neumann # define BACKBIAS_DPM_CNTL (1 << 18) 45*57e252bfSMichael Neumann # define DYN_SPREAD_SPECTRUM_EN (1 << 21) 46*57e252bfSMichael Neumann 47*57e252bfSMichael Neumann #define MCLK_PWRMGT_CNTL 0x624 48*57e252bfSMichael Neumann # define MPLL_PWRMGT_OFF (1 << 0) 49*57e252bfSMichael Neumann # define YCLK_TURNOFF (1 << 1) 50*57e252bfSMichael Neumann # define MPLL_TURNOFF (1 << 2) 51*57e252bfSMichael Neumann # define SU_MCLK_USE_BCLK (1 << 3) 52*57e252bfSMichael Neumann # define DLL_READY (1 << 4) 53*57e252bfSMichael Neumann # define MC_BUSY (1 << 5) 54*57e252bfSMichael Neumann # define MC_INT_CNTL (1 << 7) 55*57e252bfSMichael Neumann # define MRDCKA_SLEEP (1 << 8) 56*57e252bfSMichael Neumann # define MRDCKB_SLEEP (1 << 9) 57*57e252bfSMichael Neumann # define MRDCKC_SLEEP (1 << 10) 58*57e252bfSMichael Neumann # define MRDCKD_SLEEP (1 << 11) 59*57e252bfSMichael Neumann # define MRDCKE_SLEEP (1 << 12) 60*57e252bfSMichael Neumann # define MRDCKF_SLEEP (1 << 13) 61*57e252bfSMichael Neumann # define MRDCKG_SLEEP (1 << 14) 62*57e252bfSMichael Neumann # define MRDCKH_SLEEP (1 << 15) 63*57e252bfSMichael Neumann # define MRDCKA_RESET (1 << 16) 64*57e252bfSMichael Neumann # define MRDCKB_RESET (1 << 17) 65*57e252bfSMichael Neumann # define MRDCKC_RESET (1 << 18) 66*57e252bfSMichael Neumann # define MRDCKD_RESET (1 << 19) 67*57e252bfSMichael Neumann # define MRDCKE_RESET (1 << 20) 68*57e252bfSMichael Neumann # define MRDCKF_RESET (1 << 21) 69*57e252bfSMichael Neumann # define MRDCKG_RESET (1 << 22) 70*57e252bfSMichael Neumann # define MRDCKH_RESET (1 << 23) 71*57e252bfSMichael Neumann # define DLL_READY_READ (1 << 24) 72*57e252bfSMichael Neumann # define USE_DISPLAY_GAP (1 << 25) 73*57e252bfSMichael Neumann # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 74*57e252bfSMichael Neumann # define USE_DISPLAY_GAP_CTXSW (1 << 27) 75*57e252bfSMichael Neumann # define MPLL_TURNOFF_D2 (1 << 28) 76*57e252bfSMichael Neumann # define USE_DISPLAY_URGENT_CTXSW (1 << 29) 77*57e252bfSMichael Neumann 78*57e252bfSMichael Neumann #define MPLL_FREQ_LEVEL_0 0x6e8 79*57e252bfSMichael Neumann # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0) 80*57e252bfSMichael Neumann # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) 81*57e252bfSMichael Neumann # define LEVEL0_MPLL_FB_DIV(x) ((x) << 8) 82*57e252bfSMichael Neumann # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8) 83*57e252bfSMichael Neumann # define LEVEL0_MPLL_REF_DIV(x) ((x) << 20) 84*57e252bfSMichael Neumann # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20) 85*57e252bfSMichael Neumann # define LEVEL0_MPLL_DIV_EN (1 << 28) 86*57e252bfSMichael Neumann # define LEVEL0_DLL_BYPASS (1 << 29) 87*57e252bfSMichael Neumann # define LEVEL0_DLL_RESET (1 << 30) 88*57e252bfSMichael Neumann 89*57e252bfSMichael Neumann #define VID_RT 0x6f8 90*57e252bfSMichael Neumann # define VID_CRT(x) ((x) << 0) 91*57e252bfSMichael Neumann # define VID_CRT_MASK (0x1fff << 0) 92*57e252bfSMichael Neumann # define VID_CRTU(x) ((x) << 13) 93*57e252bfSMichael Neumann # define VID_CRTU_MASK (7 << 13) 94*57e252bfSMichael Neumann # define SSTU(x) ((x) << 16) 95*57e252bfSMichael Neumann # define SSTU_MASK (7 << 16) 96*57e252bfSMichael Neumann # define VID_SWT(x) ((x) << 19) 97*57e252bfSMichael Neumann # define VID_SWT_MASK (0x1f << 19) 98*57e252bfSMichael Neumann # define BRT(x) ((x) << 24) 99*57e252bfSMichael Neumann # define BRT_MASK (0xff << 24) 100*57e252bfSMichael Neumann 101*57e252bfSMichael Neumann #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c 102*57e252bfSMichael Neumann # define TARGET_PROFILE_INDEX_MASK (3 << 0) 103*57e252bfSMichael Neumann # define TARGET_PROFILE_INDEX_SHIFT 0 104*57e252bfSMichael Neumann # define CURRENT_PROFILE_INDEX_MASK (3 << 2) 105*57e252bfSMichael Neumann # define CURRENT_PROFILE_INDEX_SHIFT 2 106*57e252bfSMichael Neumann # define DYN_PWR_ENTER_INDEX(x) ((x) << 4) 107*57e252bfSMichael Neumann # define DYN_PWR_ENTER_INDEX_MASK (3 << 4) 108*57e252bfSMichael Neumann # define DYN_PWR_ENTER_INDEX_SHIFT 4 109*57e252bfSMichael Neumann # define CURR_MCLK_INDEX_MASK (3 << 6) 110*57e252bfSMichael Neumann # define CURR_MCLK_INDEX_SHIFT 6 111*57e252bfSMichael Neumann # define CURR_SCLK_INDEX_MASK (0x1f << 8) 112*57e252bfSMichael Neumann # define CURR_SCLK_INDEX_SHIFT 8 113*57e252bfSMichael Neumann # define CURR_VID_INDEX_MASK (3 << 13) 114*57e252bfSMichael Neumann # define CURR_VID_INDEX_SHIFT 13 115*57e252bfSMichael Neumann 116*57e252bfSMichael Neumann #define VID_UPPER_GPIO_CNTL 0x740 117*57e252bfSMichael Neumann # define CTXSW_UPPER_GPIO_VALUES(x) ((x) << 0) 118*57e252bfSMichael Neumann # define CTXSW_UPPER_GPIO_VALUES_MASK (7 << 0) 119*57e252bfSMichael Neumann # define HIGH_UPPER_GPIO_VALUES(x) ((x) << 3) 120*57e252bfSMichael Neumann # define HIGH_UPPER_GPIO_VALUES_MASK (7 << 3) 121*57e252bfSMichael Neumann # define MEDIUM_UPPER_GPIO_VALUES(x) ((x) << 6) 122*57e252bfSMichael Neumann # define MEDIUM_UPPER_GPIO_VALUES_MASK (7 << 6) 123*57e252bfSMichael Neumann # define LOW_UPPER_GPIO_VALUES(x) ((x) << 9) 124*57e252bfSMichael Neumann # define LOW_UPPER_GPIO_VALUES_MASK (7 << 9) 125*57e252bfSMichael Neumann # define CTXSW_BACKBIAS_VALUE (1 << 12) 126*57e252bfSMichael Neumann # define HIGH_BACKBIAS_VALUE (1 << 13) 127*57e252bfSMichael Neumann # define MEDIUM_BACKBIAS_VALUE (1 << 14) 128*57e252bfSMichael Neumann # define LOW_BACKBIAS_VALUE (1 << 15) 129*57e252bfSMichael Neumann 130*57e252bfSMichael Neumann #define CG_DISPLAY_GAP_CNTL 0x7dc 131*57e252bfSMichael Neumann # define DISP1_GAP(x) ((x) << 0) 132*57e252bfSMichael Neumann # define DISP1_GAP_MASK (3 << 0) 133*57e252bfSMichael Neumann # define DISP2_GAP(x) ((x) << 2) 134*57e252bfSMichael Neumann # define DISP2_GAP_MASK (3 << 2) 135*57e252bfSMichael Neumann # define VBI_TIMER_COUNT(x) ((x) << 4) 136*57e252bfSMichael Neumann # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 137*57e252bfSMichael Neumann # define VBI_TIMER_UNIT(x) ((x) << 20) 138*57e252bfSMichael Neumann # define VBI_TIMER_UNIT_MASK (7 << 20) 139*57e252bfSMichael Neumann # define DISP1_GAP_MCHG(x) ((x) << 24) 140*57e252bfSMichael Neumann # define DISP1_GAP_MCHG_MASK (3 << 24) 141*57e252bfSMichael Neumann # define DISP2_GAP_MCHG(x) ((x) << 26) 142*57e252bfSMichael Neumann # define DISP2_GAP_MCHG_MASK (3 << 26) 143*57e252bfSMichael Neumann 144*57e252bfSMichael Neumann #define CG_THERMAL_CTRL 0x7f0 145*57e252bfSMichael Neumann # define DPM_EVENT_SRC(x) ((x) << 0) 146*57e252bfSMichael Neumann # define DPM_EVENT_SRC_MASK (7 << 0) 147*57e252bfSMichael Neumann # define THERM_INC_CLK (1 << 3) 148*57e252bfSMichael Neumann # define TOFFSET(x) ((x) << 4) 149*57e252bfSMichael Neumann # define TOFFSET_MASK (0xff << 4) 150*57e252bfSMichael Neumann # define DIG_THERM_DPM(x) ((x) << 12) 151*57e252bfSMichael Neumann # define DIG_THERM_DPM_MASK (0xff << 12) 152*57e252bfSMichael Neumann # define CTF_SEL(x) ((x) << 20) 153*57e252bfSMichael Neumann # define CTF_SEL_MASK (7 << 20) 154*57e252bfSMichael Neumann # define CTF_PAD_POLARITY (1 << 23) 155*57e252bfSMichael Neumann # define CTF_PAD_EN (1 << 24) 156*57e252bfSMichael Neumann 157*57e252bfSMichael Neumann #define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820 158*57e252bfSMichael Neumann # define SSEN (1 << 0) 159*57e252bfSMichael Neumann # define CLKS(x) ((x) << 3) 160*57e252bfSMichael Neumann # define CLKS_MASK (0xff << 3) 161*57e252bfSMichael Neumann # define CLKS_SHIFT 3 162*57e252bfSMichael Neumann # define CLKV(x) ((x) << 11) 163*57e252bfSMichael Neumann # define CLKV_MASK (0x7ff << 11) 164*57e252bfSMichael Neumann # define CLKV_SHIFT 11 165*57e252bfSMichael Neumann #define CG_MPLL_SPREAD_SPECTRUM 0x830 166*57e252bfSMichael Neumann 167*57e252bfSMichael Neumann #define CITF_CNTL 0x200c 168*57e252bfSMichael Neumann # define BLACKOUT_RD (1 << 0) 169*57e252bfSMichael Neumann # define BLACKOUT_WR (1 << 1) 170*57e252bfSMichael Neumann 171*57e252bfSMichael Neumann #define RAMCFG 0x2408 172*57e252bfSMichael Neumann #define NOOFBANK_SHIFT 0 173*57e252bfSMichael Neumann #define NOOFBANK_MASK 0x00000001 174*57e252bfSMichael Neumann #define NOOFRANK_SHIFT 1 175*57e252bfSMichael Neumann #define NOOFRANK_MASK 0x00000002 176*57e252bfSMichael Neumann #define NOOFROWS_SHIFT 2 177*57e252bfSMichael Neumann #define NOOFROWS_MASK 0x0000001C 178*57e252bfSMichael Neumann #define NOOFCOLS_SHIFT 5 179*57e252bfSMichael Neumann #define NOOFCOLS_MASK 0x00000060 180*57e252bfSMichael Neumann #define CHANSIZE_SHIFT 7 181*57e252bfSMichael Neumann #define CHANSIZE_MASK 0x00000080 182*57e252bfSMichael Neumann #define BURSTLENGTH_SHIFT 8 183*57e252bfSMichael Neumann #define BURSTLENGTH_MASK 0x00000100 184*57e252bfSMichael Neumann #define CHANSIZE_OVERRIDE (1 << 10) 185*57e252bfSMichael Neumann 186*57e252bfSMichael Neumann #define SQM_RATIO 0x2424 187*57e252bfSMichael Neumann # define STATE0(x) ((x) << 0) 188*57e252bfSMichael Neumann # define STATE0_MASK (0xff << 0) 189*57e252bfSMichael Neumann # define STATE1(x) ((x) << 8) 190*57e252bfSMichael Neumann # define STATE1_MASK (0xff << 8) 191*57e252bfSMichael Neumann # define STATE2(x) ((x) << 16) 192*57e252bfSMichael Neumann # define STATE2_MASK (0xff << 16) 193*57e252bfSMichael Neumann # define STATE3(x) ((x) << 24) 194*57e252bfSMichael Neumann # define STATE3_MASK (0xff << 24) 195*57e252bfSMichael Neumann 196*57e252bfSMichael Neumann #define ARB_RFSH_CNTL 0x2460 197*57e252bfSMichael Neumann # define ENABLE (1 << 0) 198*57e252bfSMichael Neumann #define ARB_RFSH_RATE 0x2464 199*57e252bfSMichael Neumann # define POWERMODE0(x) ((x) << 0) 200*57e252bfSMichael Neumann # define POWERMODE0_MASK (0xff << 0) 201*57e252bfSMichael Neumann # define POWERMODE1(x) ((x) << 8) 202*57e252bfSMichael Neumann # define POWERMODE1_MASK (0xff << 8) 203*57e252bfSMichael Neumann # define POWERMODE2(x) ((x) << 16) 204*57e252bfSMichael Neumann # define POWERMODE2_MASK (0xff << 16) 205*57e252bfSMichael Neumann # define POWERMODE3(x) ((x) << 24) 206*57e252bfSMichael Neumann # define POWERMODE3_MASK (0xff << 24) 207*57e252bfSMichael Neumann 208*57e252bfSMichael Neumann #define MC_SEQ_DRAM 0x2608 209*57e252bfSMichael Neumann # define CKE_DYN (1 << 12) 210*57e252bfSMichael Neumann 211*57e252bfSMichael Neumann #define MC_SEQ_CMD 0x26c4 212*57e252bfSMichael Neumann 213*57e252bfSMichael Neumann #define MC_SEQ_RESERVE_S 0x2890 214*57e252bfSMichael Neumann #define MC_SEQ_RESERVE_M 0x2894 215*57e252bfSMichael Neumann 216*57e252bfSMichael Neumann #define LVTMA_DATA_SYNCHRONIZATION 0x7adc 217*57e252bfSMichael Neumann # define LVTMA_PFREQCHG (1 << 8) 218*57e252bfSMichael Neumann #define DCE3_LVTMA_DATA_SYNCHRONIZATION 0x7f98 219*57e252bfSMichael Neumann 220*57e252bfSMichael Neumann /* PCIE indirect regs */ 221*57e252bfSMichael Neumann #define PCIE_P_CNTL 0x40 222*57e252bfSMichael Neumann # define P_PLL_PWRDN_IN_L1L23 (1 << 3) 223*57e252bfSMichael Neumann # define P_PLL_BUF_PDNB (1 << 4) 224*57e252bfSMichael Neumann # define P_PLL_PDNB (1 << 9) 225*57e252bfSMichael Neumann # define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12) 226*57e252bfSMichael Neumann /* PCIE PORT indirect regs */ 227*57e252bfSMichael Neumann #define PCIE_LC_CNTL 0xa0 228*57e252bfSMichael Neumann # define LC_L0S_INACTIVITY(x) ((x) << 8) 229*57e252bfSMichael Neumann # define LC_L0S_INACTIVITY_MASK (0xf << 8) 230*57e252bfSMichael Neumann # define LC_L0S_INACTIVITY_SHIFT 8 231*57e252bfSMichael Neumann # define LC_L1_INACTIVITY(x) ((x) << 12) 232*57e252bfSMichael Neumann # define LC_L1_INACTIVITY_MASK (0xf << 12) 233*57e252bfSMichael Neumann # define LC_L1_INACTIVITY_SHIFT 12 234*57e252bfSMichael Neumann # define LC_PMI_TO_L1_DIS (1 << 16) 235*57e252bfSMichael Neumann # define LC_ASPM_TO_L1_DIS (1 << 24) 236*57e252bfSMichael Neumann #define PCIE_LC_SPEED_CNTL 0xa4 237*57e252bfSMichael Neumann # define LC_GEN2_EN (1 << 0) 238*57e252bfSMichael Neumann # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 7) 239*57e252bfSMichael Neumann # define LC_CURRENT_DATA_RATE (1 << 11) 240*57e252bfSMichael Neumann # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 241*57e252bfSMichael Neumann # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 242*57e252bfSMichael Neumann # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 243*57e252bfSMichael Neumann # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 244*57e252bfSMichael Neumann # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 245*57e252bfSMichael Neumann 246*57e252bfSMichael Neumann #endif 247