| /freebsd-src/sys/contrib/device-tree/src/arm/amlogic/ |
| H A D | meson6.dtsi | 51 clocks = <&xtal>, <&clk81>;
52 clock-names = "xtal", "pclk";
56 clocks = <&xtal>, <&clk81>, <&clk81>;
57 clock-names = "xtal", "pclk", "baud";
61 clocks = <&xtal>, <&clk81>, <&clk81>;
62 clock-names = "xtal", "pclk", "baud";
66 clocks = <&xtal>, <&clk81>, <&clk81>;
67 clock-names = "xtal", "pclk", "baud";
71 clocks = <&xtal>, <&clk81>, <&clk81>;
72 clock-names = "xtal", "pclk", "baud";
|
| H A D | meson8.dtsi | 256 clocks = <&xtal>;
257 clock-names = "xtal";
581 xtal_32k_out_pins: xtal-32k-out {
584 function = "xtal";
630 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
631 clock-names = "xtal", "ddr_pll";
718 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
727 clocks = <&xtal>,
753 clocks = <&xtal>, <&clkc CLKID_CLK81>;
754 clock-names = "xtal", "pcl
[all...] |
| H A D | meson8b.dtsi | 233 clocks = <&xtal>;
234 clock-names = "xtal";
591 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
592 clock-names = "xtal", "ddr_pll";
693 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
702 clocks = <&xtal>,
724 clocks = <&xtal>, <&clkc CLKID_CLK81>;
725 clock-names = "xtal", "pclk";
730 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
731 clock-names = "xtal", "pcl
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | armada3700-xtal-clock.txt | 1 * Xtal Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
12 "marvell,armada-3700-xtal-clock"
17 output names ("xtal")
24 xtalclk: xtal-clk {
25 compatible = "marvell,armada-3700-xtal-clock";
26 clock-output-names = "xtal";
|
| H A D | silabs,si5351.txt | 23 handles, shall be xtal reference clock or xtal and clkin for
24 si5351c only. Corresponding clock input names are "xtal" and
46 2 = xtal
78 /* connect xtal input to 25MHz reference */
80 clock-names = "xtal";
82 /* connect xtal input as source of pll0 and pll1 */
119 * - xtal as clock source of output divider
|
| H A D | amlogic,gxbb-clkc.txt | 17 * "xtal": the platform xtal
40 clocks = <&xtal>;
41 clock-names = "xtal";
|
| H A D | silabs,si5351.yaml | 50 - const: xtal
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
106 2 - use XTAL for this output
212 /* Connect XTAL input to 25MHz reference */
214 clock-names = "xtal";
216 /* Use XTAL input as source of PLL0 and PLL1 */
258 * - XTAL as clock source of output divider
|
| H A D | marvell,armada-3700-uart-clock.yaml | 23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
28 used for UART (most probably xtal) for smooth boot log on UART.
36 - const: xtal
57 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
|
| H A D | amlogic,gxbb-aoclkc.txt | 17 * "xtal" : the platform xtal
51 clocks = <&xtal>, <&clkc CLKID_CLK81>;
52 clock-names = "xtal", "mpeg-clk";
|
| H A D | nxp,lpc3220-clk.txt | 11 "xtal_32k" and may have optional "xtal"
27 clocks = <&xtal_32k>, <&xtal>;
28 clock-names = "xtal_32k", "xtal";
|
| H A D | amlogic,s4-pll-clkc.yaml | 25 - const: xtal
44 clocks = <&xtal>;
45 clock-names = "xtal";
|
| H A D | amlogic,meson8-ddr-clkc.yaml | 26 - const: xtal
45 clocks = <&xtal>;
46 clock-names = "xtal";
|
| /freebsd-src/sys/contrib/device-tree/src/arm64/amlogic/ |
| H A D | amlogic-t7-a311d2-an400.dts | 27 xtal: xtal-clk { label
30 clock-output-names = "xtal";
36 clocks = <&xtal>, <&xtal>, <&xtal>;
37 clock-names = "xtal", "pclk", "baud";
|
| H A D | amlogic-t7-a311d2-khadas-vim4.dts | 41 xtal: xtal-clk { label
44 clock-output-names = "xtal";
52 clocks = <&xtal>, <&xtal>, <&xtal>;
53 clock-names = "xtal", "pclk", "baud";
|
| H A D | amlogic-c3.dtsi | 49 xtal: xtal-clk {
52 clock-output-names = "xtal";
122 clocks = <&xtal>,
165 clocks = <&xtal>;
441 <&xtal>,
548 clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_B>, <&xtal>;
549 clock-names = "xtal", "pclk", "baud";
43 xtal: xtal-clk { global() label
|
| H A D | meson-gxbb.dtsi | 286 clocks = <&xtal>, <&clkc CLKID_CLK81>;
287 clock-names = "xtal", "mpeg-clk";
322 assigned-clock-parents = <&xtal>, <0>;
330 clocks = <&xtal>;
331 clock-names = "xtal";
789 clocks = <&xtal>,
838 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
839 clock-names = "xtal", "pclk", "baud";
843 clocks = <&xtal>, <
[all...] |
| H A D | meson-a1.dtsi | 306 <&xtal>;
309 "hifi_pll", "xtal";
328 clocks = <&xtal>, <&xtal>, <&xtal>;
329 clock-names = "xtal", "pclk", "baud";
338 clocks = <&xtal>, <&xtal>, <&xtal>;
339 clock-names = "xtal", "pcl
512 xtal: xtal-clk { global() label
[all...] |
| H A D | meson-gxl.dtsi | 310 clocks = <&xtal>, <&clkc CLKID_CLK81>;
311 clock-names = "xtal", "mpeg-clk";
334 assigned-clock-parents = <&xtal>, <0>;
342 clocks = <&xtal>;
343 clock-names = "xtal";
859 clocks = <&xtal>,
908 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
909 clock-names = "xtal", "pclk", "baud";
913 clocks = <&xtal>, <
[all...] |
| H A D | meson-s4.dtsi | 62 xtal: xtal-clk {
65 clock-output-names = "xtal";
121 <&xtal>;
125 "mpll2", "mpll3", "hdmi_pll", "xtal";
132 clocks = <&xtal>;
133 clock-names = "xtal";
140 clocks = <&xtal>;
606 <&xtal>,
755 clocks = <&xtal>, <
61 xtal: xtal-clk { global() label
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/serial/ |
| H A D | amlogic,meson-uart.yaml | 70 - description: external xtal clock identifier
72 - description: the source of the baudrate generator, can be either the xtal or the pclk
76 - const: xtal
100 clocks = <&xtal>, <&pclk>, <&xtal>;
101 clock-names = "xtal", "pclk", "baud";
|
| /freebsd-src/sys/contrib/device-tree/Bindings/timer/ |
| H A D | amlogic,meson6-timer.txt | 8 - clocks : phandles to the pclk (system clock) and XTAL clocks
9 - clock-names : must contain "pclk" and "xtal"
20 clocks = <&xtal>, <&clk81>;
21 clock-names = "xtal", "pclk";
|
| H A D | amlogic,meson6-timer.yaml | 29 - const: xtal
52 clocks = <&xtal>, <&clk81>;
53 clock-names = "xtal", "pclk";
|
| /freebsd-src/sys/arm/mv/clk/ |
| H A D | periph_clk_d.c | 55 * or xtal output) -> gate (enable or disable clock), which is also final node
97 parent_names[0] = device_def->common_def.xtal; in a37x0_periph_d_register_full_clk_dd()
119 * mux (select divided freq. or xtal output) -> gate (enable or disable clock),
153 parent_names[0] = device_def->common_def.xtal; in a37x0_periph_d_register_full_clk()
175 * divider) -> mux (choose divided or xtal output).
206 parent_names[0] = device_def->common_def.xtal; in a37x0_periph_d_register_periph_cpu()
220 * div2 (second frequency divider) -> mux (choose divided or xtal output).
259 parent_names[0] = device_def->common_def.xtal; in a37x0_periph_d_register_mdd()
|
| /freebsd-src/sys/contrib/device-tree/Bindings/soc/amlogic/ |
| H A D | amlogic,meson-gx-hhi-sysctrl.yaml | 111 clocks = <&xtal>;
112 clock-names = "xtal";
156 clocks = <&xtal>, <&clk81>;
157 clock-names = "xtal", "mpeg-clk";
170 clocks = <&xtal>;
171 clock-names = "xtal";
|
| /freebsd-src/sys/contrib/device-tree/Bindings/net/ieee802154/ |
| H A D | at86rf230.txt | 15 - xtal-trim: u8 value for fine tuning the internal capacitance
16 arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF
26 xtal-trim = /bits/ 8 <0x06>;
|