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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,vic.txt5 nested or have the outputs wire-OR'd together.
9 - compatible : should be one of
10 "arm,pl190-vic"
11 "arm,pl192-vic"
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
16 - reg : The register bank for the VIC.
20 - interrupts : Interrupt source for parent controllers if the VIC is nested.
21 - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
24 clear means otherwise. If unspecified, defaults to all valid.
[all …]
H A Darm,vic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
23 - arm,pl190-vic
24 - arm,pl192-vic
25 - arm,versatile-vic
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H A Dbrcm,bcm7038-l1-intc.txt1 Broadcom BCM7038-style Level 1 interrupt controller
4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
9 - 64, 96, 128, or 160 incoming level IRQ lines
11 - Most onchip peripherals are wired directly to an L1 input
13 - A separate instance of the register set for each CPU, allowing individual
16 - Atomic mask/unmask operations
18 - No polarity/level/edge settings
20 - No FIFO or priority encoder logic; software is expected to read all
21 2-5 status words to determine which IRQs are pending
25 - compatible: should be "brcm,bcm7038-l1-intc"
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H A Dbrcm,bcm7038-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
23 - Atomic mask/unmask operations
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H A Dbrcm,bcm7120-l2-intc.txt1 Broadcom BCM7120-style Level 2 interrupt controller
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
20 - not all bits within the interrupt controller actually map to an interrupt
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
27 \-----------\
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
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/freebsd-src/sys/contrib/device-tree/src/arm/samsung/
H A Ds3c6400.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 valid-mask = <0xfffffe1f>;
24 valid-wakeup-mask = <0x00200004>;
28 valid-mask = <0xffffffff>;
29 valid-wakeup-mask = <0x53020000>;
33 clocks: clock-controller@7e00f000 {
34 compatible = "samsung,s3c6400-clock";
36 #clock-cells = <1>;
H A Ds3c6410.dtsi1 // SPDX-License-Identifier: GPL-2.0
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
37 clocks: clock-controller@7e00f000 {
38 compatible = "samsung,s3c6410-clock";
40 #clock-cells = <1>;
44 compatible = "samsung,s3c2440-i2c";
46 interrupt-parent = <&vic0>;
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/freebsd-src/sys/contrib/dev/iwlwifi/fw/api/
H A Dd3.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
9 #include <iwl-tran
188 u8 mask[IWL_WOWLAN_MAX_PATTERN_LEN / 8]; global() member
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/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dmediatek,mtu3.txt4 - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
5 soc-model is the name of SoC, such as mt8173, mt2712 etc,
8 - "mediatek,mt8173-mtu3"
9 - reg : specifies physical base address and size of the registers
10 - reg-names: should be "mac" for device IP and "ippc" for IP port control
11 - interrupts : interrupt used by the device IP
12 - power-domains : a phandle to USB power domain node to control USB's
14 - vusb33-supply : regulator of USB avdd3.3v
15 - clocks : a list of phandle + clock-specifier pairs, one for each
16 entry in clock-names
[all …]
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/dev/rtw89/
H A Dwow.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
17 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; in rtw89_wow_leave_deep_ps()
18 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; in rtw89_wow_leave_deep_ps()
19 const u8 *rsn, *ies = mgmt->u.assoc_req.variable;
22 rsn = cfg80211_find_ie(WLAN_EID_RSN, ies, skb->le in rtw89_wow_enter_deep_ps()
88 struct cfg80211_wowlan_wakeup wakeup = { rtw89_wow_show_wakeup_reason() local
253 const u8 *mask; rtw89_wow_pattern_generate() local
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/freebsd-src/sys/dev/igc/
H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
14 /* Definitions for power management and wakeup registers */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enabl
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H A Digc_regs.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
11 #define IGC_CTRL 0x00000 /* Device Control - RW */
12 #define IGC_STATUS 0x00008 /* Device Status - RO */
13 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
15 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
16 #define IGC_EEWR 0x12018 /* EEprom mode write - R
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/freebsd-src/sys/dev/e1000/
H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 /* Definitions for power management and wakeup registers */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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H A De1000_phy.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
68 * Setups up the function pointers to no-op functions
72 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_ops_generic()
76 phy->ops.init_params = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
77 phy->op in e1000_init_phy_ops_generic()
2175 u16 phy_data, offset, mask; e1000_check_downshift_generic() local
2247 u16 data, offset, mask; e1000_check_polarity_igp() local
2290 u16 phy_data, offset, mask; e1000_check_polarity_ife() local
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H A De1000_regs.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 #define E1000_CTRL 0x00000 /* Device Control - RW */
39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
40 #define E1000_STATUS 0x00008 /* Device Status - RO */
41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
44 #define E1000_FLA 0x0001C /* Flash Access - RW */
45 #define E1000_MDIC 0x00020 /* MDI Control - RW */
[all …]
/freebsd-src/sys/contrib/dev/athk/ath10k/
H A Dwow.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2015-2017 Qualcomm Atheros, Inc.
14 #include "wmi-ops.h"
26 struct ath10k *ar = arvif->ar; in ath10k_wow_vif_cleanup()
30 ret = ath10k_wmi_wow_add_wakeup_event(ar, arvif->vdev_id, i, 0); in ath10k_wow_vif_cleanup()
32 ath10k_warn(ar, "failed to issue wow wakeup for event %s on vdev %i: %d\n", in ath10k_wow_vif_cleanup()
33 wow_wakeup_event(i), arvif->vdev_id, ret); in ath10k_wow_vif_cleanup()
38 for (i = 0; i < ar->wow.max_num_patterns; i++) { in ath10k_wow_vif_cleanup()
39 ret = ath10k_wmi_wow_del_pattern(ar, arvif->vdev_id, i); in ath10k_wow_vif_cleanup()
42 i, arvif->vdev_id, ret); in ath10k_wow_vif_cleanup()
[all …]
/freebsd-src/sys/contrib/dev/athk/ath11k/
H A Dwow.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
34 clear_bit(ATH11K_FLAG_HTC_SUSPEND_COMPLETE, &ab->dev_flags); in ath11k_wow_enable()
37 reinit_completion(&ab->htc_suspend); in ath11k_wow_enable()
45 ret = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ); in ath11k_wow_enable()
49 return -ETIMEDOUT; in ath11k_wow_enable()
52 if (test_bit(ATH11K_FLAG_HTC_SUSPEND_COMPLETE, &ab->dev_flags)) in ath11k_wow_enable()
63 return -ETIMEDOUT; in ath11k_wow_enable()
71 /* In the case of WCN6750, WoW wakeup is done in ath11k_wow_wakeup()
75 if (ab->hw_params.smp2p_wow_exit) in ath11k_wow_wakeup()
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/freebsd-src/sys/dev/tpm/
H A Dtpm.c3 * Copyright (c) 2009, 2010 Hans-Joerg Hoexer
49 #define IRQUNK -1
58 #define TPM_ACCESS_VALID 0x80 /* bits are valid */
60 "\020\01EST\02REQ\03PEND\04SEIZE\05SEIZED\06ACT\010VALID"
83 #define TPM_INTF_INT_LEVEL_LOW 0x0010 /* level-low ints supported */
84 #define TPM_INTF_INT_LEVEL_HIGH 0x0008 /* level-high ints supported */
85 #define TPM_INTF_LOCALITY_CHANGE_INT 0x0004 /* locality-change int (mb 1) */
96 #define TPM_STS_VALID 0x00000080 /* ro other bits are valid */
102 #define TPM_STS_BITS "\020\010VALID\07RDY\06GO\05DRDY\04EXPECT\02RETRY"
128 ((struct tpm_softc *)dev->si_drv1)
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H A Dtpm_tis_core.c1 /*-
91 uint32_t mask, uint32_t val, int32_t timeout);
102 sc->dev = dev; in tpmtis_attach()
103 sc->intr_type = -1; in tpmtis_attach()
105 sx_init(&sc->dev_lock, "TPM driver lock"); in tpmtis_attach()
106 sc->buf = malloc(TPM_BUFSIZE, M_TPM20, M_WAITOK); in tpmtis_attach()
108 sc->irq_rid = 0; in tpmtis_attach()
109 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, in tpmtis_attach()
111 if (sc->irq_res == NULL) in tpmtis_attach()
114 result = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, in tpmtis_attach()
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/freebsd-src/sys/contrib/dev/iwlwifi/mvm/
H A Dd3.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
17 #include "iwl-modparam
1432 bool valid; global() member
1453 struct cfg80211_wowlan_wakeup wakeup = { iwl_mvm_report_wakeup_reasons() local
2578 struct cfg80211_wowlan_wakeup wakeup = { iwl_mvm_query_netdetect_reasons() local
2684 u32 valid; iwl_mvm_rt_status() member
2709 struct cfg80211_wowlan_wakeup wakeup = { iwl_mvm_check_rt_status() local
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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…
513 …t by primary CPU as part of the initialization process will initiate power-on-reset to this specif…
[all …]
/freebsd-src/lib/libthr/thread/
H A Dthr_exit.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1995-1998 John Birrell <jb@cimlogic.com.au>
15 * 3. Neither the name of the author nor the names of any co-contributors
43 #include "un-namespace.h"
83 * Make sure the address is always valid by holding the library, in thread_uw_init()
146 cfa >= (uintptr_t)curthread->unwind_stackend) { in thread_unwind_stop()
150 while ((cur = curthread->cleanup) != NULL && in thread_unwind_stop()
156 /* Tell libc that it should call non-trivial TLS dtors. */ in thread_unwind_stop()
170 curthread->ex.exception_class = 0; in thread_unwind()
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/freebsd-src/sys/dev/usb/
H A Dusb_hub.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2008-2022 Hans Petter Selasky
108 #define UHUB_PROTO(sc) ((sc)->sc_udev->ddesc.bDeviceProtocol)
198 usb_needs_explore(sc->sc_udev->bus, 0); in uhub_intr_callback()
206 if (xfer->error != USB_ERR_CANCELLED) { in uhub_intr_callback()
208 * Do a clear-stall. The "stall_pipe" flag in uhub_intr_callback()
220 /*------------------------------------------------------------------------*
224 *------------------------------------------------------------------------*/
230 struct usb_device *udev = pm->udev; in uhub_reset_tt_proc()
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/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_power.c30 ahp->ah_mcast_filter_l32_set = 0; in ar9300_wowoffload_prep()
31 ahp->ah_mcast_filter_u32_set = 0; in ar9300_wowoffload_prep()
39 if (ahp->ah_mcast_filter_l32_set != 0) { in ar9300_wowoffload_post()
41 val &= ~ahp->ah_mcast_filter_l32_set; in ar9300_wowoffload_post()
44 if (ahp->ah_mcast_filter_u32_set != 0) { in ar9300_wowoffload_post()
46 val &= ~ahp->ah_mcast_filter_u32_set; in ar9300_wowoffload_post()
50 ahp->ah_mcast_filter_l32_set = 0; in ar9300_wowoffload_post()
51 ahp->ah_mcast_filter_u32_set = 0; in ar9300_wowoffload_post()
72 ahp->ah_mcast_filter_u32_set |= (1 << pos); in ar9300_wowoffload_add_mcast_filter()
74 ahp->ah_mcast_filter_l32_set |= (1 << pos); in ar9300_wowoffload_add_mcast_filter()
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