Lines Matching +full:valid +full:- +full:wakeup +full:- +full:mask
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
14 /* Definitions for power management and wakeup registers */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
29 #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
90 #define IGC_RXD_STAT_IPIDV 0x200 /* IP identification valid */
91 #define IGC_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
107 /* Same mask, but for extended and packet split descriptors */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
160 /* these buffer sizes are valid if IGC_RCTL_BSEX is 0 */
165 /* these buffer sizes are valid if IGC_RCTL_BSEX is 1 */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
218 #define IGC_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
246 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
279 /* 1000/H is not supported, nor spec-compliant. */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
346 /* GPY211 - I225 defines */
487 /* This defines the bits that are set in the Interrupt Mask
502 /* Interrupt Mask Set */
507 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
508 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
520 /* Extended Interrupt Mask Set */
581 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
605 /* Loop limit on how long we wait for auto-negotiation to complete */
618 #define IGC_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
619 #define IGC_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
626 #define IGC_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
627 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
630 #define IGC_RXCW_CW 0x0000ffff /* RxConfigWord mask */
635 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
638 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
639 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
671 /* Time Sync Interrupt Cause/Mask Register Bits */
743 #define IGC_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
745 #define IGC_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
754 #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
755 #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
756 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
759 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
881 /* 1000BASE-T Control Register */
897 /* 1000BASE-T Status Register */
920 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
921 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
949 #define IGC_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
957 #define IGC_EECD_SEC1VAL_I225 0x02000000 /* Sector One Valid */
959 #define IGC_FWSM_FW_VALID_I225 0x8000 /* FW valid bit */
1008 /* Mask bits for fields in Word 0x0f of the NVM */
1013 /* Mask bits for fields in Word 0x1a of the NVM */
1016 /* Mask bits for fields in Word 0x03 of the EEPROM */
1031 /* NVM Commands - Microwire */
1038 /* NVM Commands - SPI */
1042 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1070 /* PCI/PCI-X/PCI-EX Config space */
1096 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1099 /* Bit definitions for valid PHY IDs.
1129 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1140 * 1 = 50-80M
1141 * 2 = 80-110M
1142 * 3 = 110-140M
1171 * 15-5: page
1172 * 4-0: register offset
1190 /* Page 193 - Port Control Registers */
1195 /* Page 194 - KMRN Registers */
1209 #define IGC_N0_QUEUE -1
1231 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1260 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1264 /* Minimum time for 100BASE-T where no data will be transmit following move out
1356 #define IGC_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */