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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp1 //===- AggressiveAntiDepBreaker.cpp - Anti-dep breaker -------
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H A DCriticalAntiDepBreaker.cpp1 //===- CriticalAntiDepBreaker.cpp - Anti-dep breaker ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // implements register anti-dependence breaking along a blocks
11 // critical path during post-RA scheduler.
13 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "post-RA-sched"
44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
45 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
46 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker()
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H A DRegAllocFast.cpp1 //===- RegAllocFast.cpp - A fast register allocator for debug code --------
189 const TargetRegisterInfo *TRI = nullptr; global() member in __anon279642bd0111::RegAllocFast
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H A DFixupStatepointCallerSaved.cpp1 //===-- FixupStatepointCallerSaved.cpp - Fixup caller saved registers ----===//
5 // SPDX-License-Identifier: Apache-2.
92 getRegisterSize(const TargetRegisterInfo & TRI,Register Reg) getRegisterSize() argument
113 performCopyPropagation(Register Reg,MachineBasicBlock::iterator & RI,bool & IsKill,const TargetInstrInfo & TII,const TargetRegisterInfo & TRI) performCopyPropagation() argument
211 const TargetRegisterInfo &TRI; global() member in __anon44967f430211::FrameIndexesCache
235 FrameIndexesCache(MachineFrameInfo & MFI,const TargetRegisterInfo & TRI) FrameIndexesCache() argument
319 const TargetRegisterInfo &TRI; global() member in __anon44967f430211::StatepointState
566 const TargetRegisterInfo &TRI; global() member in __anon44967f430211::StatepointProcessor
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H A DCallingConvLower.cpp1 //===-- CallingConvLower.cpp - Calling Conventions ------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
32 TRI(*MF.getSubtarget().getRegisterInfo()), Locs(Locs), Context(Context), in CCState()
39 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
55 MF.getSubtarget().getTargetLowering()->HandleByVal(this, Size, Alignment); in HandleByVal()
63 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) in MarkAllocated()
68 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) in MarkUnallocated()
77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
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H A DMachineVerifier.cpp1 //===- MachineVerifier.cpp - Machine Code Verifier --------
108 const TargetRegisterInfo *TRI = nullptr; global() member
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H A DAggressiveAntiDepBreaker.h1 //==- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // implements register anti-dependence breaking during post-RA
11 // scheduling. It attempts to break all anti-dependencies within a
14 //===----------------------------------------------------------------------===//
39 /// Contains all the state necessary for anti-dep breaking.
52 /// Number of non-virtual target registers (i.e. TRI->getNumRegs()).
55 /// Implements a disjoint-union data structure to
65 /// composed of registers that are not eligible for anti-aliasing.
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H A DRegisterPressure.cpp1 //===- RegisterPressure.cpp - Dynamic Register Pressure --------
82 dumpRegSetPressure(ArrayRef<unsigned> SetPressure,const TargetRegisterInfo * TRI) dumpRegSetPressure() argument
226 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); init() local
470 const TargetRegisterInfo &TRI; global() member in __anona4fb94840611::RegisterOperandsCollector
475 RegisterOperandsCollector(RegisterOperands & RegOpers,const TargetRegisterInfo & TRI,const MachineRegisterInfo & MRI,bool IgnoreDead) RegisterOperandsCollector() argument
568 collect(const MachineInstr & MI,const TargetRegisterInfo & TRI,const MachineRegisterInfo & MRI,bool TrackLaneMasks,bool IgnoreDead) collect() argument
1225 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); findUseBetween() local
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H A DProcessImplicitDefs.cpp1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
31 const TargetRegisterInfo *TRI = nullptr; member in __anon5d738d620111::ProcessImplicitDefs
70 if (!MI->isCopyLike() && in canTurnIntoImplicitDef()
71 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
72 !MI->isRegSequence() && in canTurnIntoImplicitDef()
73 !MI->isPHI()) in canTurnIntoImplicitDef()
75 for (const MachineOperand &MO : MI->all_uses()) in canTurnIntoImplicitDef()
83 Register Reg = MI->getOperand(0).getReg(); in processImplicitDef()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls -------
456 hasHazard(StateT State,function_ref<HazardFnResult (StateT &,const MachineInstr &)> IsHazard,function_ref<void (StateT &,const MachineInstr &)> UpdateState,const MachineBasicBlock * MBB,MachineBasicBlock::const_reverse_instr_iterator I,DenseSet<const MachineBasicBlock * > & Visited) hasHazard() argument
570 const SIRegisterInfo *TRI = ST.getRegisterInfo(); getWaitStatesSinceDef() local
592 addRegUnits(const SIRegisterInfo & TRI,BitVector & BV,MCRegister Reg) addRegUnits() argument
598 addRegsToSet(const SIRegisterInfo & TRI,iterator_range<MachineInstr::const_mop_iterator> Ops,BitVector & DefSet,BitVector & UseSet) addRegsToSet() argument
740 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkDPPHazards() local
864 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazardsHelper() local
893 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazards() local
929 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazards() local
953 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkVALUHazards() local
1050 const SIRegisterInfo *TRI = ST.getRegisterInfo(); checkRWLaneHazards() local
1113 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVcmpxPermlaneHazards() local
1155 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVMEMtoScalarWriteHazards() local
1211 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixSMEMtoVectorWriteHazards() local
1286 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixVcmpxExecWARHazard() local
1534 StateType State; fixVALUPartialForwardingHazard() local
1537 __anon7fc9b90f2702(StateType &State, const MachineInstr &I) fixVALUPartialForwardingHazard() argument
1621 __anon7fc9b90f2802(StateType &State, const MachineInstr &MI) fixVALUPartialForwardingHazard() argument
1671 StateType State; fixVALUTransUseHazard() local
1674 __anon7fc9b90f2902(StateType &State, const MachineInstr &I) fixVALUTransUseHazard() argument
1697 __anon7fc9b90f2a02(StateType &State, const MachineInstr &MI) fixVALUTransUseHazard() argument
1723 const SIRegisterInfo *TRI = ST.getRegisterInfo(); fixWMMAHazards() local
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H A DAMDGPUInsertDelayAlu.cpp1 //===- AMDGPUInsertDelayAlu.cpp - Insert s_delay_alu instructions ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
22 #define DEBUG_TYPE "amdgpu-insert-delay-alu"
31 const TargetRegisterInfo *TRI; member in __anon4f1322a90111::AMDGPUInsertDelayAlu
74 // regunit. In straight-line code there will only be one such instruction, but
76 // to represent the union of the worst-case delays of each type.
78 // One larger than the maximum number of (non-TRANS) VALU instructions we
90 // If it was written by a (non-TRANS) VALU, remember how many clock cycles
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H A DSIWholeQuadMode.cpp1 //===-- SIWholeQuadMode.cpp - enter and suspend whole quad mode -------
101 int State; global() member
112 char State = PS.State; operator <<() local
153 const SIRegisterInfo *TRI; global() member in __anonc8fda5900111::SIWholeQuadMode
1080 char State = BI.InitialState; lowerBlock() local
1316 char State = (IsEntry || !(BI.InNeeds & StateWQM)) ? StateExact : StateWQM; processBlock() local
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H A DSIFormMemoryClauses.cpp1 //===-- SIFormMemoryClauses.cpp --------
71 const SIRegisterInfo *TRI; global() member in __anon9a5ae0de0111::SIFormMemoryClauses
231 unsigned State = getMopState(MO); collectRegUses() local
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H A DGCNNSAReassign.cpp1 //===-- GCNNSAReassign.cpp - Reassign registers in NSA instructions -------
71 const SIRegisterInfo *TRI; global() member in __anon4c4f99bb0111::GCNNSAReassign
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kCollapseMOVEMPass.cpp1 //===-- M68kCollapseMOVEMPass.cpp - Expand MOVEM pass -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "m68k-collapse-movem"
114 } else if (Type == Descending && O == Start - 4) { in update()
115 Start -= 4; in update()
163 const M68kRegisterInfo *TRI; member in __anon3bad31010111::M68kCollapseMOVEM
169 void Finish(MachineBasicBlock &MBB, MOVEMState &State) { in Finish() argument
170 auto MI = State.begin(); in Finish()
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/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-bindings.txt4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
15 need to reconfigure pins at run-time, for example to tri-state pins when the
21 for client device device tree nodes to map those state names to the pin
25 For example, a pin controller may set up its own "active" state when the
35 For each client device individually, every pin state is assigned an integer
36 ID. These numbers start at 0, and are contiguous. For each state ID, a unique
37 property exists to define the pin configuration. Each state may also be
42 defined in its device tree node, and whether to define the set of state
43 IDs that must be provided, or whether to define the set of state names that
47 pinctrl-0: List of phandles, each pointing at a pin configuration
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H A Dnvidia,tegra20-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-pinmux
19 - description: tri-state registers
20 - description: mux register
21 - description: pull-up/down registers
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H A Dnvidia,tegra20-pinmux.txt4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
38 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp1 //===--- AArch64CallLowering.cpp - Call lowering ------
833 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo(); doCallerAndCalleePassArgsTheSameWay() local
886 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo(); areCalleeOutgoingArgsTailCallable() local
1032 getMaskForArgs(SmallVectorImpl<AArch64CallLowering::ArgInfo> & OutArgs,AArch64CallLowering::CallLoweringInfo & Info,const AArch64RegisterInfo & TRI,MachineFunction & MF) getMaskForArgs() argument
1089 auto TRI = Subtarget.getRegisterInfo(); lowerTailCall() local
1316 const auto *TRI = Subtarget.getRegisterInfo(); lowerCall() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.cpp1 //=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
31 CCState &State) { in CC_X86_32_RegCall_Assign2Regs() argument
42 if (!State.isAllocated(Reg)) in CC_X86_32_RegCall_Assign2Regs()
48 return false; // Not enough free registers - continue the search. in CC_X86_32_RegCall_Assign2Regs()
54 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_X86_32_RegCall_Assign2Regs()
64 // Successful in allocating registers - stop scanning next rules. in CC_X86_32_RegCall_Assign2Regs()
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H A DX86SpeculativeLoadHardening.cpp1 //====- X86SpeculativeLoadHardening.cpp - A Spectre v1 mitigation --------
164 const TargetRegisterInfo *TRI = nullptr; global() member in __anonc37902080111::X86SpeculativeLoadHardeningPass
1212 isEFLAGSLive(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const TargetRegisterInfo & TRI) isEFLAGSLive() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp1 //===- ResourcePriorityQueue.cpp - A DFA-oriented priority queue -*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // SchedulingPriorityQueue that prioritizes instructions using DFA state to
13 // The scheduler is basically a top-down adaptable list scheduler with DFA
15 // DFA is queried as a state machine to model "packets/bundles" during
19 //===----------------------------------------------------------------------===//
36 DisableDFASched("disable-dfa-sched", cl::Hidden,
40 "dfa-sched-reg-pressure-threshold", cl::Hidden, cl::init(5),
41 cl::desc("Track reg pressure and switch priority to in-depth"));
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H A DScheduleDAGRRList.cpp1 //===- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler ------===//
5 // SPDX-License-Identifie
313 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter & RegDefPos,const TargetLowering * TLI,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI,unsigned & RegClass,unsigned & Cost,const MachineFunction & MF) GetCostForDef() argument
1298 CheckForLiveRegDef(SUnit * SU,unsigned Reg,SUnit ** LiveRegDefs,SmallSet<unsigned,4> & RegAdded,SmallVectorImpl<unsigned> & LRegs,const TargetRegisterInfo * TRI,const SDNode * Node=nullptr) CheckForLiveRegDef() argument
1744 const TargetRegisterInfo *TRI = nullptr; global() member in __anon9cef1bc00311::RegReductionPQBase
1764 RegReductionPQBase(MachineFunction & mf,bool hasReadyFilter,bool tracksrp,bool srcorder,const TargetInstrInfo * tii,const TargetRegisterInfo * tri,const TargetLowering * tli) RegReductionPQBase() argument
1890 RegReductionPriorityQueue(MachineFunction & mf,bool tracksrp,bool srcorder,const TargetInstrInfo * tii,const TargetRegisterInfo * tri,const TargetLowering * tli) RegReductionPriorityQueue() argument
2859 canClobberReachingPhysRegUse(const SUnit * DepSU,const SUnit * SU,ScheduleDAGRRList * scheduleDAG,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) canClobberReachingPhysRegUse() argument
2894 canClobberPhysRegDefs(const SUnit * SuccSU,const SUnit * SU,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) canClobberPhysRegDefs() argument
3149 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); createBURRListDAGScheduler() local
3163 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); createSourceListDAGScheduler() local
3177 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); createHybridListDAGScheduler() local
3192 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); createILPListDAGScheduler() local
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h1 //===- llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h -------*- C++ -*
47 executeMatchTable(TgtExecutor & Exec,MatcherState & State,const ExecInfoTy<PredicateBitset,ComplexMatcherMemFn,CustomRendererFn> & ExecInfo,MachineIRBuilder & Builder,const uint8_t * MatchTable,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI,const PredicateBitset & AvailableFeatures,CodeGenCoverage * CoverageInfo) executeMatchTable() argument
52 executeMatchTable(TgtExecutor & Exec,MatcherState & State,const ExecInfoTy<PredicateBitset,ComplexMatcherMemFn,CustomRendererFn> & ExecInfo,MachineIRBuilder & Builder,const uint8_t * MatchTable,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI,const PredicateBitset & AvailableFeatures,CodeGenCoverage * CoverageInfo) executeMatchTable() argument
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/freebsd-src/contrib/libcxxrt/
H A Dguard.cc2 * Copyright 2010-2012 PathScale, Inc. All rights reserved.
29 * guard.cc: Functions for thread-safe static initialisation.
37 * Statics that require initialisation are protected by a 64-bit value. Any
38 * platform that can do 32-bit atomic test and set operations can use this
39 * value as a low-overhead lock. Because statics (in most sane code) are
57 // x86 and ARM are the most common little-endian CPUs, so let's have a
66 * The Itanium C++ ABI defines guard words that are 64-bit (32-bit on AArch32)
71 * On many 32-bit platforms, 64-bit atomics are unavailable (or slow) and so we
72 * treat the two halves of the 64-bit word as independent values and establish
74 * lock word is in the locked state. This means that we can do double-checked
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