xref: /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ProcessImplicitDefs.cpp (revision 06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e)
10b57cec5SDimitry Andric //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric 
90b57cec5SDimitry Andric #include "llvm/ADT/SetVector.h"
100b57cec5SDimitry Andric #include "llvm/Analysis/AliasAnalysis.h"
110b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunctionPass.h"
120b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstr.h"
130b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
140b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h"
150b57cec5SDimitry Andric #include "llvm/CodeGen/TargetSubtargetInfo.h"
16480093f4SDimitry Andric #include "llvm/InitializePasses.h"
1781ad6265SDimitry Andric #include "llvm/Pass.h"
1881ad6265SDimitry Andric #include "llvm/PassRegistry.h"
190b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
200b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
210b57cec5SDimitry Andric 
220b57cec5SDimitry Andric using namespace llvm;
230b57cec5SDimitry Andric 
240b57cec5SDimitry Andric #define DEBUG_TYPE "processimpdefs"
250b57cec5SDimitry Andric 
260b57cec5SDimitry Andric namespace {
270b57cec5SDimitry Andric /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
280b57cec5SDimitry Andric /// for each use. Add isUndef marker to implicit_def defs and their uses.
290b57cec5SDimitry Andric class ProcessImplicitDefs : public MachineFunctionPass {
30*06c3fb27SDimitry Andric   const TargetInstrInfo *TII = nullptr;
31*06c3fb27SDimitry Andric   const TargetRegisterInfo *TRI = nullptr;
32*06c3fb27SDimitry Andric   MachineRegisterInfo *MRI = nullptr;
330b57cec5SDimitry Andric 
340b57cec5SDimitry Andric   SmallSetVector<MachineInstr*, 16> WorkList;
350b57cec5SDimitry Andric 
360b57cec5SDimitry Andric   void processImplicitDef(MachineInstr *MI);
370b57cec5SDimitry Andric   bool canTurnIntoImplicitDef(MachineInstr *MI);
380b57cec5SDimitry Andric 
390b57cec5SDimitry Andric public:
400b57cec5SDimitry Andric   static char ID;
410b57cec5SDimitry Andric 
ProcessImplicitDefs()420b57cec5SDimitry Andric   ProcessImplicitDefs() : MachineFunctionPass(ID) {
430b57cec5SDimitry Andric     initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
440b57cec5SDimitry Andric   }
450b57cec5SDimitry Andric 
460b57cec5SDimitry Andric   void getAnalysisUsage(AnalysisUsage &au) const override;
470b57cec5SDimitry Andric 
480b57cec5SDimitry Andric   bool runOnMachineFunction(MachineFunction &MF) override;
4981ad6265SDimitry Andric 
getRequiredProperties() const50972a253aSDimitry Andric   MachineFunctionProperties getRequiredProperties() const override {
5181ad6265SDimitry Andric     return MachineFunctionProperties().set(
5281ad6265SDimitry Andric         MachineFunctionProperties::Property::IsSSA);
5381ad6265SDimitry Andric   }
540b57cec5SDimitry Andric };
550b57cec5SDimitry Andric } // end anonymous namespace
560b57cec5SDimitry Andric 
570b57cec5SDimitry Andric char ProcessImplicitDefs::ID = 0;
580b57cec5SDimitry Andric char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
590b57cec5SDimitry Andric 
600b57cec5SDimitry Andric INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
610b57cec5SDimitry Andric                 "Process Implicit Definitions", false, false)
620b57cec5SDimitry Andric 
getAnalysisUsage(AnalysisUsage & AU) const630b57cec5SDimitry Andric void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
640b57cec5SDimitry Andric   AU.setPreservesCFG();
650b57cec5SDimitry Andric   AU.addPreserved<AAResultsWrapperPass>();
660b57cec5SDimitry Andric   MachineFunctionPass::getAnalysisUsage(AU);
670b57cec5SDimitry Andric }
680b57cec5SDimitry Andric 
canTurnIntoImplicitDef(MachineInstr * MI)690b57cec5SDimitry Andric bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
700b57cec5SDimitry Andric   if (!MI->isCopyLike() &&
710b57cec5SDimitry Andric       !MI->isInsertSubreg() &&
720b57cec5SDimitry Andric       !MI->isRegSequence() &&
730b57cec5SDimitry Andric       !MI->isPHI())
740b57cec5SDimitry Andric     return false;
75*06c3fb27SDimitry Andric   for (const MachineOperand &MO : MI->all_uses())
76*06c3fb27SDimitry Andric     if (MO.readsReg())
770b57cec5SDimitry Andric       return false;
780b57cec5SDimitry Andric   return true;
790b57cec5SDimitry Andric }
800b57cec5SDimitry Andric 
processImplicitDef(MachineInstr * MI)810b57cec5SDimitry Andric void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
820b57cec5SDimitry Andric   LLVM_DEBUG(dbgs() << "Processing " << *MI);
838bcb0991SDimitry Andric   Register Reg = MI->getOperand(0).getReg();
840b57cec5SDimitry Andric 
85bdd1243dSDimitry Andric   if (Reg.isVirtual()) {
860b57cec5SDimitry Andric     // For virtual registers, mark all uses as <undef>, and convert users to
870b57cec5SDimitry Andric     // implicit-def when possible.
880b57cec5SDimitry Andric     for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
890b57cec5SDimitry Andric       MO.setIsUndef();
900b57cec5SDimitry Andric       MachineInstr *UserMI = MO.getParent();
910b57cec5SDimitry Andric       if (!canTurnIntoImplicitDef(UserMI))
920b57cec5SDimitry Andric         continue;
930b57cec5SDimitry Andric       LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
940b57cec5SDimitry Andric       UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
950b57cec5SDimitry Andric       WorkList.insert(UserMI);
960b57cec5SDimitry Andric     }
970b57cec5SDimitry Andric     MI->eraseFromParent();
980b57cec5SDimitry Andric     return;
990b57cec5SDimitry Andric   }
1000b57cec5SDimitry Andric 
1010b57cec5SDimitry Andric   // This is a physreg implicit-def.
1020b57cec5SDimitry Andric   // Look for the first instruction to use or define an alias.
1030b57cec5SDimitry Andric   MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
1040b57cec5SDimitry Andric   MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
1050b57cec5SDimitry Andric   bool Found = false;
1060b57cec5SDimitry Andric   for (++UserMI; UserMI != UserE; ++UserMI) {
1070b57cec5SDimitry Andric     for (MachineOperand &MO : UserMI->operands()) {
1080b57cec5SDimitry Andric       if (!MO.isReg())
1090b57cec5SDimitry Andric         continue;
1108bcb0991SDimitry Andric       Register UserReg = MO.getReg();
111bdd1243dSDimitry Andric       if (!UserReg.isPhysical() || !TRI->regsOverlap(Reg, UserReg))
1120b57cec5SDimitry Andric         continue;
1130b57cec5SDimitry Andric       // UserMI uses or redefines Reg. Set <undef> flags on all uses.
1140b57cec5SDimitry Andric       Found = true;
1150b57cec5SDimitry Andric       if (MO.isUse())
1160b57cec5SDimitry Andric         MO.setIsUndef();
1170b57cec5SDimitry Andric     }
1180b57cec5SDimitry Andric     if (Found)
1190b57cec5SDimitry Andric       break;
1200b57cec5SDimitry Andric   }
1210b57cec5SDimitry Andric 
1220b57cec5SDimitry Andric   // If we found the using MI, we can erase the IMPLICIT_DEF.
1230b57cec5SDimitry Andric   if (Found) {
1240b57cec5SDimitry Andric     LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
1250b57cec5SDimitry Andric     MI->eraseFromParent();
1260b57cec5SDimitry Andric     return;
1270b57cec5SDimitry Andric   }
1280b57cec5SDimitry Andric 
1290b57cec5SDimitry Andric   // Using instr wasn't found, it could be in another block.
1300b57cec5SDimitry Andric   // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
1310b57cec5SDimitry Andric   for (unsigned i = MI->getNumOperands() - 1; i; --i)
13281ad6265SDimitry Andric     MI->removeOperand(i);
1330b57cec5SDimitry Andric   LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
1340b57cec5SDimitry Andric }
1350b57cec5SDimitry Andric 
1360b57cec5SDimitry Andric /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
1370b57cec5SDimitry Andric /// <undef> operands.
runOnMachineFunction(MachineFunction & MF)1380b57cec5SDimitry Andric bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
1390b57cec5SDimitry Andric 
1400b57cec5SDimitry Andric   LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
1410b57cec5SDimitry Andric                     << "********** Function: " << MF.getName() << '\n');
1420b57cec5SDimitry Andric 
1430b57cec5SDimitry Andric   bool Changed = false;
1440b57cec5SDimitry Andric 
1450b57cec5SDimitry Andric   TII = MF.getSubtarget().getInstrInfo();
1460b57cec5SDimitry Andric   TRI = MF.getSubtarget().getRegisterInfo();
1470b57cec5SDimitry Andric   MRI = &MF.getRegInfo();
1480b57cec5SDimitry Andric   assert(WorkList.empty() && "Inconsistent worklist state");
1490b57cec5SDimitry Andric 
150fe6060f1SDimitry Andric   for (MachineBasicBlock &MBB : MF) {
1510b57cec5SDimitry Andric     // Scan the basic block for implicit defs.
152fe6060f1SDimitry Andric     for (MachineInstr &MI : MBB)
153fe6060f1SDimitry Andric       if (MI.isImplicitDef())
154fe6060f1SDimitry Andric         WorkList.insert(&MI);
1550b57cec5SDimitry Andric 
1560b57cec5SDimitry Andric     if (WorkList.empty())
1570b57cec5SDimitry Andric       continue;
1580b57cec5SDimitry Andric 
159fe6060f1SDimitry Andric     LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size()
1600b57cec5SDimitry Andric                       << " implicit defs.\n");
1610b57cec5SDimitry Andric     Changed = true;
1620b57cec5SDimitry Andric 
1630b57cec5SDimitry Andric     // Drain the WorkList to recursively process any new implicit defs.
1640b57cec5SDimitry Andric     do processImplicitDef(WorkList.pop_back_val());
1650b57cec5SDimitry Andric     while (!WorkList.empty());
1660b57cec5SDimitry Andric   }
1670b57cec5SDimitry Andric   return Changed;
1680b57cec5SDimitry Andric }
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