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/llvm-project/llvm/test/Transforms/DeadStoreElimination/
H A Dinst-limits.ll13 ; The first store; later there is a second store to the same location,
19 %0 = bitcast i32 0 to i32
20 %1 = bitcast i32 0 to i32
21 %2 = bitcast i32 0 to i32
22 %3 = bitcast i32 0 to i32
23 %4 = bitcast i32 0 to i32
24 %5 = bitcast i32 0 to i32
25 %6 = bitcast i32 0 to i32
26 %7 = bitcast i32 0 to i32
27 %8 = bitcast i32 0 to i32
[all …]
/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
H A Dfp-cast.ll7 ; extracts, due to the undef operands.
10 %v0 = fpext double undef to fp128
11 %v1 = fpext float undef to fp128
12 %v2 = fpext float undef to double
13 %v3 = fpext <2 x double> undef to <2 x fp128>
14 %v4 = fpext <2 x float> undef to <2 x fp128>
15 %v5 = fpext <2 x float> undef to <2 x double>
16 %v6 = fpext <4 x double> undef to <4 x fp128>
17 %v7 = fpext <4 x float> undef to <4 x fp128>
18 %v8 = fpext <4 x float> undef to <4 x double>
[all …]
H A Dint-cast.ll4 %v0 = sext i8 undef to i16
5 %v1 = sext i8 undef to i32
6 %v2 = sext i8 undef to i64
7 %v3 = sext i16 undef to i32
8 %v4 = sext i16 undef to i64
9 %v5 = sext i32 undef to i64
10 %v6 = sext <2 x i8> undef to <2 x i16>
11 %v7 = sext <2 x i8> undef to <2 x i32>
12 %v8 = sext <2 x i8> undef to <2 x i64>
13 %v9 = sext <2 x i16> undef to <2 x i32>
[all …]
/llvm-project/libcxx/test/std/concepts/concepts.lang/concept.derived/
H A Dderived_from.pass.cpp28 template <typename From, typename To>
31 static_assert(!std::derived_from<From*, To>); in CheckNotDerivedFromPointer()
32 static_assert(!std::derived_from<From*, const To>); in CheckNotDerivedFromPointer()
33 static_assert(!std::derived_from<From*, volatile To>); in CheckNotDerivedFromPointer()
34 static_assert(!std::derived_from<From*, const volatile To>); in CheckNotDerivedFromPointer()
36 if constexpr (!std::same_as<To, void>) { in CheckNotDerivedFromPointer()
37 static_assert(!std::derived_from<From*, To&>); in CheckNotDerivedFromPointer()
38 static_assert(!std::derived_from<From*, const To&>); in CheckNotDerivedFromPointer()
39 static_assert(!std::derived_from<From*, volatile To&>); in CheckNotDerivedFromPointer()
40 static_assert(!std::derived_from<From*, const volatile To&>); in CheckNotDerivedFromPointer()
[all …]
/llvm-project/llvm/test/Analysis/CostModel/RISCV/
H A Dcast.ll7 ; RV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_v2i16 = sext <2 x i8> undef to <2 x i16>
8 ; RV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_v2i32 = sext <2 x i8> undef to <2 x i32>
9 ; RV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_v2i64 = sext <2 x i8> undef to <2 x i64>
10 ; RV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16_v2i32 = sext <2 x i16> undef to <2 x i32>
11 ; RV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16_v2i64 = sext <2 x i16> undef to <2 x i64>
12 ; RV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32_v2i64 = sext <2 x i32> undef to <2 x i64>
13 ; RV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i1_v2i8 = sext <2 x i1> undef to <2 x i8>
14 ; RV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i1_v2i16 = sext <2 x i1> undef to <2 x i16>
15 ; RV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i1_v2i32 = sext <2 x i1> undef to <2 x i32>
16 ; RV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i1_v2i64 = sext <2 x i1> undef to <
[all...]
/llvm-project/clang/test/OpenMP/
H A Dtarget_update_to_messages.cpp71 …to(*this) // le45-error {{expected expression containing only member accesses and/or array section… in foo()
73 …to(*(this->ptr)) // le45-error {{expected expression containing only member accesses and/or array … in foo()
74 …to(*(this->S->i+this->S->p)) // le45-error {{expected expression containing only member accesses a… in foo()
75 …to(*(this->S->i+this->S->s6[0].pp)) // le45-error {{expected expression containing only member acc… in foo()
76 …to(*(a+this->ptr)) // le45-error {{expected expression containing only member accesses and/or arra… in foo()
77 …to(*(*(this->ptr)+a+this->ptr)) // le45-error {{expected expression containing only member accesse… in foo()
78 #pragma omp target update to(*(this+this)) // expected-error {{invalid operands to binary expressio… in foo()
82 …to(marr [0:1][2:4][1:2]) // le45-error {{array section does not specify contiguous storage}} le45-… in foo()
104 T to; in tmain() local
108 …rget update to // expected-error {{expected '(' after 'to'}} expected-error {{expected at least on… in tmain()
[all …]
/llvm-project/clang/test/SemaCXX/
H A Dwarn-tautological-undefined-compare.cpp9 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in test1()
11 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in test1()
19 …er cannot be null in well-defined C++ code; comparison may be assumed to always evaluate to false}} in foo()
21 …ter cannot be null in well-defined C++ code; comparison may be assumed to always evaluate to true}} in foo()
27 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in bar()
29 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in bar()
49 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in test()
51 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in test()
54 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in test()
56 …eference cannot be bound to dereferenced null pointer in well-defined C++ code; comparison may be … in test()
[all …]
/llvm-project/llvm/test/Analysis/CostModel/X86/
H A Dtrunc-latency.ll20 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i32
21 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
22 …st Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
23 …st Model: Found an estimated cost of 4 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
24 …Model: Found an estimated cost of 8 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
28 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i32
29 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
30 …st Model: Found an estimated cost of 1 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
31 …st Model: Found an estimated cost of 1 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
32 …Model: Found an estimated cost of 1 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
[all …]
H A Dtrunc-codesize.ll20 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i32
21 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
22 …st Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
23 …st Model: Found an estimated cost of 4 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
24 …Model: Found an estimated cost of 8 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
28 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i32
29 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
30 …st Model: Found an estimated cost of 1 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
31 …st Model: Found an estimated cost of 1 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
32 …Model: Found an estimated cost of 1 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
[all …]
H A Dtrunc-sizelatency.ll20 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i32
21 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
22 …st Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
23 …st Model: Found an estimated cost of 4 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
24 …Model: Found an estimated cost of 8 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
28 ; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i32
29 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
30 …st Model: Found an estimated cost of 1 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
31 …st Model: Found an estimated cost of 1 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
32 …Model: Found an estimated cost of 1 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
[all …]
H A Dtrunc.ll20 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i32
21 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
22 …st Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
23 …st Model: Found an estimated cost of 4 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
24 …Model: Found an estimated cost of 8 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
28 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i64 = trunc i64 undef to i…
29 …st Model: Found an estimated cost of 1 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i32>
30 …st Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i32>
31 …st Model: Found an estimated cost of 5 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i32>
32 …odel: Found an estimated cost of 10 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i32>
[all …]
H A Dextend.ll20 ; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %I64 = zext i32 undef to i64
21 …ost Model: Found an estimated cost of 1 for instruction: %V2i64 = zext <2 x i32> undef to <2 x i64>
22 …ost Model: Found an estimated cost of 2 for instruction: %V4i64 = zext <4 x i32> undef to <4 x i64>
23 …ost Model: Found an estimated cost of 4 for instruction: %V8i64 = zext <8 x i32> undef to <8 x i64>
24 … Model: Found an estimated cost of 8 for instruction: %V16i64 = zext <16 x i32> undef to <16 x i64>
25 …Model: Found an estimated cost of 16 for instruction: %V32i64 = zext <32 x i32> undef to <32 x i64>
29 ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %I64 = zext i32 undef to i64
30 …ost Model: Found an estimated cost of 1 for instruction: %V2i64 = zext <2 x i32> undef to <2 x i64>
31 …ost Model: Found an estimated cost of 3 for instruction: %V4i64 = zext <4 x i32> undef to <4 x i64>
32 …ost Model: Found an estimated cost of 7 for instruction: %V8i64 = zext <8 x i32> undef to <8 x i64>
[all …]
H A Dmin-legal-vector-width.ll10 ; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %A = zext <8 x i16> undef to…
11 ; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %B = zext <8 x i32> undef to…
12 ; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %C = zext <16 x i8> undef to…
13 … Cost Model: Found an estimated cost of 3 for instruction: %D = zext <16 x i16> undef to <16 x i32>
14 ; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %E = zext <32 x i8> undef to…
18 …: Cost Model: Found an estimated cost of 2 for instruction: %A = zext <8 x i16> undef to <8 x i64>
19 …: Cost Model: Found an estimated cost of 3 for instruction: %B = zext <8 x i32> undef to <8 x i64>
20 … Cost Model: Found an estimated cost of 2 for instruction: %C = zext <16 x i8> undef to <16 x i32>
21 … Cost Model: Found an estimated cost of 3 for instruction: %D = zext <16 x i16> undef to <16 x i32>
22 … Cost Model: Found an estimated cost of 3 for instruction: %E = zext <32 x i8> undef to <32 x i16>
[all …]
/llvm-project/llvm/test/ExecutionEngine/
H A Dtest-interp-vec-cast.ll
/llvm-project/llvm/test/Other/
H A Dconstant-fold-gep.ll9 ; "TO" - Optimizations and targetdata. This tests target-dependent
11 ; RUN: opt -S -o - -passes='function(instcombine),globalopt' -data-layout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64" < %s | FileCheck --check-prefix=TO %s
21 ; PLAIN: @G8 = global ptr getelementptr (i8, ptr inttoptr (i32 1 to ptr), i32 -1)
22 ; PLAIN: @G1 = global ptr getelementptr (i1, ptr inttoptr (i32 1 to ptr), i32 -1)
23 ; PLAIN: @F8 = global ptr getelementptr (i8, ptr inttoptr (i32 1 to ptr), i32 -2)
24 ; PLAIN: @F1 = global ptr getelementptr (i1, ptr inttoptr (i32 1 to ptr), i32 -2)
29 ; OPT: @F8 = local_unnamed_addr global ptr inttoptr (i64 -1 to ptr)
30 ; OPT: @F1 = local_unnamed_addr global ptr inttoptr (i64 -1 to ptr)
31 ; OPT: @H8 = local_unnamed_addr global ptr inttoptr (i64 -1 to ptr)
32 ; OPT: @H1 = local_unnamed_addr global ptr inttoptr (i64 -1 to pt
[all...]
/llvm-project/llvm/test/ExecutionEngine/MCJIT/
H A Dtest-cast.ll10 zext i1 true to i8 ; <i8>:2 [#uses=0]
11 zext i1 true to i8 ; <i8>:3 [#uses=0]
12 zext i1 true to i16 ; <i16>:4 [#uses=0]
13 zext i1 true to i16 ; <i16>:5 [#uses=0]
14 zext i1 true to i32 ; <i32>:6 [#uses=0]
15 zext i1 true to i32 ; <i32>:7 [#uses=0]
16 zext i1 true to i64 ; <i64>:8 [#uses=0]
17 zext i1 true to i64 ; <i64>:9 [#uses=0]
18 uitofp i1 true to float ; <float>:10 [#uses=0]
19 uitofp i1 true to double ; <double>:11 [#uses=0]
[all …]
/llvm-project/clang/test/CodeGenCXX/
H A Dmicrosoft-abi-rtti.cpp149 …to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 trunc (i64 sub nuw nsw (i64 ptrtoint…
151 … (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R2B2@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)…
152 …to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 trunc (i64 sub nuw nsw (i64 ptrtoint…
153 …to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 3, i32 0, i32 -1, i32 0, i32 64, i32…
154 …to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 2, i32 0, i32 0, i32 4, i32 80, i32 …
156 … (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R2A2@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)…
157 …to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 trunc (i64 sub nuw nsw (i64 ptrtoint…
158 …to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 2, i32 0, i32 -1, i32 0, i32 64, i32…
159 …to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 0, i32 0, i32 -1, i32 0, i32 64, i32…
161 … (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R2Z2@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)…
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dint-conv-11.ll6 ; to use LLC(H) if possible.
44 %trunc0 = trunc i32 %val0 to i8
45 %trunc1 = trunc i32 %val1 to i8
46 %trunc2 = trunc i32 %val2 to i8
47 %trunc3 = trunc i32 %val3 to i8
48 %trunc4 = trunc i32 %val4 to i8
49 %trunc5 = trunc i32 %val5 to i8
50 %trunc6 = trunc i32 %val6 to i8
51 %trunc7 = trunc i32 %val7 to i8
52 %trunc8 = trunc i32 %val8 to i8
[all …]
/llvm-project/llvm/test/Analysis/CostModel/AArch64/
H A Dcast.ll10 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r0 = sext i1 undef to i8
11 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext i1 undef to i8
12 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext i1 undef to i16
13 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r3 = zext i1 undef to i16
14 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r4 = sext i1 undef to i32
15 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r5 = zext i1 undef to i32
16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r6 = sext i1 undef to i64
17 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = zext i1 undef to i64
18 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r9 = sext i8 undef to i16
19 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r10 = zext i8 undef to i1
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dframe-setup-without-sgpr-to-vgpr-spills.ll2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=true < %s | FileCheck -check-prefix=SPILL-TO-VGPR %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-spill-sgpr-to-vgpr=false < %s | FileCheck -check-prefix=NO-SPILL-TO-VGPR %s
5 ; Check frame setup where SGPR spills to VGPRs are disabled or enabled.
10 ; SPILL-TO-VGPR-LABEL: callee_with_stack_and_call:
11 ; SPILL-TO-VGPR: ; %bb.0:
12 ; SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
13 ; SPILL-TO-VGPR-NEXT: s_mov_b32 s4, s33
14 ; SPILL-TO
[all...]
/llvm-project/llvm/test/Analysis/CostModel/ARM/
H A Dcast.ll17 …ON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r0 = sext i1 undef to i8
18 …ON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r1 = zext i1 undef to i8
19 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r2 = sext i1 undef to i16
20 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = zext i1 undef to i16
21 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r4 = sext i1 undef to i32
22 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r5 = zext i1 undef to i32
23 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r6 = sext i1 undef to i64
24 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r7 = zext i1 undef to i64
25 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = trunc i8 undef to i1
26 …N-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = sext i8 undef to i16
[all …]
/llvm-project/llvm/docs/
H A DDeveloperPolicy.rst15 to eliminate miscommunication, rework, and confusion that might arise from the
17 we hope each developer can know ahead of time what to expect when making LLVM
21 This policy is also designed to accomplish the following objectives:
23 #. Attract both users and developers to the LLVM project.
30 policies <copyright-license-patents>` with contributors to the project.
32 This policy is aimed at frequent contributors to LLVM. People interested in
33 contributing one-off patches can do so in an informal way by sending them to the
36 developer to see it through the process.
41 This section contains policies that pertain to frequent LLVM developers. We
42 always welcome `one-off patches`_ from people who do not routinely contribute to
[all...]
/llvm-project/bolt/docs/
H A Ddoxygen.cfg.in3 # This file describes the settings to be used by the documentation system
37 # The PROJECT_NUMBER tag can be used to enter a project or revision number. This
52 # to the output directory.
56 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
58 # entered, it will be relative to the location where doxygen was started. If
63 # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-
73 # The OUTPUT_LANGUAGE tag is used to specify the language in which all
75 # information to generate all constant output in the proper language.
88 # If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member
90 # documentation (similar to Javadoc). Set to NO to disable this.
[all …]
/llvm-project/polly/docs/
H A Ddoxygen.cfg.in3 # This file describes the settings to be used by the documentation system
37 # The PROJECT_NUMBER tag can be used to enter a project or revision number. This
52 # to the output directory.
56 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
58 # entered, it will be relative to the location where doxygen was started. If
63 # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-
73 # The OUTPUT_LANGUAGE tag is used to specify the language in which all
75 # information to generate all constant output in the proper language.
88 # If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member
90 # documentation (similar to Javado
[all...]
/llvm-project/flang/docs/
H A Ddoxygen.cfg.in3 # This file describes the settings to be used by the documentation system
37 # The PROJECT_NUMBER tag can be used to enter a project or revision number. This
52 # to the output directory.
56 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
58 # entered, it will be relative to the location where doxygen was started. If
63 # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-
73 # The OUTPUT_LANGUAGE tag is used to specify the language in which all
75 # information to generate all constant output in the proper language.
88 # If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member
90 # documentation (similar to Javadoc). Set to NO to disable this.
[all …]

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