Searched full:slcr (Results 1 – 15 of 15) sorted by relevance
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.113 /* Unlock SLCR with magic number. */ in zy7_slcr_unlock() 121 /* Lock SLCR with magic number. */ in zy7_slcr_lock() 130 /* Unlock SLCR registers. */ in zy7_slcr_cpu_reset() 159 /* Unlock SLCR registers. */ in zy7_slcr_preload_pl() 168 /* Lock SLCR registers. */ in zy7_slcr_preload_pl() 189 /* Unlock SLCR registers. */ in zy7_slcr_postload_pl() 199 /* Lock SLCR registers. */ in zy7_slcr_postload_pl() 235 /* Unlock SLCR registers. */ in cgem_set_ref_clk() 245 /* Lock SLCR register in cgem_set_ref_clk() [all...]
66 /* Map in SLCR PSS_IDCODE register. */ in zynq7_mp_setmaxid()69 panic("%s: Could not map SLCR IDCODE reg.\n", __func__); in zynq7_mp_setmaxid()
61 /* SLCR, PS system, and CPU private registers combined in this region. */
30 * Defines for Zynq-7000 SLCR registers.36 * (v1.4) November 16, 2012. Xilinx doc UG585. SLCR register definitions
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>10 - syscon: <&slcr>11 This should be a phandle to the Zynq's SLCR registers.14 The Zynq Reset Manager needs to be a childnode of the SLCR.21 syscon = <&slcr>;
9 - syscon: phandle for access to SLCR registers18 syscon = <&slcr>;
32 Phandle to syscon block which provide access to SLCR registers51 syscon = <&slcr>;
357 syscon = <&slcr>;
5 - syscon: phandle to SLCR6 - reg: Offset and length of pinctrl space in SLCR81 syscon = <&slcr>;
34 description: Specifies the base address and size of the SLCR space.39 phandle to the SLCR.186 syscon = <&slcr>;
310 slcr: slcr@f8000000 { label313 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";338 syscon = <&slcr>;344 syscon = <&slcr>;373 syscon = <&slcr>;
47 // SLCR block48 slcr: slcr@7000 { label
46 &slcr {
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >