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/freebsd-src/sys/contrib/device-tree/Bindings/iommu/
H A Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
13 "qcom,msm8953-iommu"
15 Followed by "qcom,msm-iommu-v1".
17 - clock-names : Should be a pair of "iface" (required for IOMMUs
18 register group access) and "bus" (required for
19 the IOMMUs underlying bus access).
[all …]
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robi
[all...]
H A Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
23 By default, the access issuing initiator is informed about the error
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/nvmem/
H A Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-rome
[all...]
H A Dqcom,sec-qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc, Secure QFPROM Efuse
10 - Komal Bajaj <quic_kbajaj@quicinc.com>
14 protected from non-secure access. In such situations, the OS have to use
15 secure calls to read the region.
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
[all...]
H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
[all …]
H A Dcci.txt5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
[all …]
H A Darm,scmi.txt2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
34 - interrupts : when using smc or hvc transports, this optional
[all …]
H A Darm,scpi.txt2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
[all …]
/freebsd-src/contrib/wpa/hostapd/
H A DREADME-WPS1 hostapd and Wi-Fi Protected Setup (WPS)
10 -------------------
12 Wi-Fi Protected Setup (WPS) is a mechanism for easy configuration of a
14 passphrase/PSK) and configuration of an access point and client
16 with PIN method and push-button configuration (PBC) being the most
22 not very secure. As such, use of WPS may not be suitable for
23 environments that require secure network access without chance for
24 allowing outsiders to gain access during the setup phase.
28 - access point: the WLAN access point
29 - Registrar: a device that control a network and can authorize
[all …]
/freebsd-src/sys/arm64/vmm/io/
H A Dvgic_v3.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (C) 2020-2022 Andrew Turner
79 #define VGIC_SGI_NUM (GIC_LAST_SGI - GIC_FIRST_SGI + 1)
80 #define VGIC_PPI_NUM (GIC_LAST_PPI - GIC_FIRST_PPI + 1)
81 #define VGIC_SPI_NUM (GIC_LAST_SPI - GIC_FIRST_SPI + 1)
127 /* Per-CP
636 gic_pidr2_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) gic_pidr2_read() argument
644 gic_zero_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) gic_zero_read() argument
651 gic_ignore_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) gic_ignore_write() argument
992 dist_ctlr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_ctlr_read() argument
1010 dist_ctlr_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_ctlr_write() argument
1039 dist_typer_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_typer_read() argument
1054 dist_iidr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_iidr_read() argument
1061 dist_setclrspi_nsr_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_setclrspi_nsr_write() argument
1075 dist_isenabler_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_isenabler_read() argument
1086 dist_isenabler_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_isenabler_write() argument
1101 dist_icenabler_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_icenabler_read() argument
1112 dist_icenabler_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_icenabler_write() argument
1127 dist_ispendr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_ispendr_read() argument
1138 dist_ispendr_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_ispendr_write() argument
1153 dist_icpendr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_icpendr_read() argument
1164 dist_icpendr_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_icpendr_write() argument
1180 dist_isactiver_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_isactiver_read() argument
1191 dist_isactiver_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_isactiver_write() argument
1206 dist_icactiver_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_icactiver_read() argument
1218 dist_icactiver_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_icactiver_write() argument
1234 dist_ipriorityr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_ipriorityr_read() argument
1246 dist_ipriorityr_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_ipriorityr_write() argument
1259 dist_icfgr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_icfgr_read() argument
1270 dist_icfgr_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_icfgr_write() argument
1285 dist_irouter_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) dist_irouter_read() argument
1296 dist_irouter_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) dist_irouter_write() argument
1309 vgic_register_read(struct hypctx * hypctx,struct vgic_register * reg_list,u_int reg_list_size,u_int reg,u_int size,uint64_t * rval,void * arg) vgic_register_read() argument
1344 vgic_register_write(struct hypctx * hypctx,struct vgic_register * reg_list,u_int reg_list_size,u_int reg,u_int size,uint64_t wval,void * arg) vgic_register_write() argument
1375 uint64_t reg; dist_read() local
1413 uint64_t reg; dist_write() local
1447 redist_ctlr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_ctlr_read() argument
1455 redist_iidr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_iidr_read() argument
1462 redist_typer_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_typer_read() argument
1499 redist_ienabler0_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_ienabler0_read() argument
1506 redist_isenabler0_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_isenabler0_write() argument
1516 redist_icenabler0_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_icenabler0_write() argument
1526 redist_ipendr0_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_ipendr0_read() argument
1533 redist_ispendr0_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_ispendr0_write() argument
1543 redist_icpendr0_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_icpendr0_write() argument
1553 redist_iactiver0_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_iactiver0_read() argument
1560 redist_isactiver0_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_isactiver0_write() argument
1568 redist_icactiver0_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_icactiver0_write() argument
1576 redist_ipriorityr_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_ipriorityr_read() argument
1586 redist_ipriorityr_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_ipriorityr_write() argument
1597 redist_icfgr1_read(struct hypctx * hypctx,u_int reg,uint64_t * rval,void * arg) redist_icfgr1_read() argument
1603 redist_icfgr1_write(struct hypctx * hypctx,u_int reg,u_int offset,u_int size,uint64_t wval,void * arg) redist_icfgr1_write() argument
1618 uint64_t reg; redist_read() local
1696 uint64_t reg; redist_write() local
2085 uint64_t reg; vgic_v3_inject_msi() local
[all...]
/freebsd-src/sys/arm/arm/
H A Dgeneric_timer.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
36 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
89 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
90 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg acces
289 int reg; cntpct_handler() local
[all...]
H A Dcpuinfo.c1 /*-
61 * Be careful, ACTRL cannot be changed if CPU is started in secure
80 uint32_t reg; in sysctl_hw_cpu_quirks_actrl_value() local
82 reg = cp15_actlr_get(); in sysctl_hw_cpu_quirks_actrl_value()
83 return (SYSCTL_OUT(req, &reg, sizeof(reg))); in sysctl_hw_cpu_quirks_actrl_value()
127 /* non ARM -> must be new id scheme */ in cpuinfo_init()
136 /* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */ in cpuinfo_init()
161 /* Not yet - CBAR only exist on ARM SMP Cortex A CPUs in cpuinfo_init()
203 cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1; in cpuinfo_init()
204 cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1; in cpuinfo_init()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/interconnect/
H A Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
17 ("Global Programmers View") but not all. Access to this area might be denied
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
21 available for video and other secure applications, as well as DRAM ECC for
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3-tao3530.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
10 /* Secure omaps have some devices inaccessible depending on the firmware */
26 cpu0-supply = <&vcc>;
32 reg = <0x80000000 0x10000000>; /* 256 MB */
37 compatible = "regulator-fixed";
38 regulator-name = "hsusb2_vbus";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
[all …]
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controlle
[all...]
H A Domap3-n900.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
7 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-binding
[all...]
/freebsd-src/sys/arm64/nvidia/tegra210/
H A Dtegra210_pmc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
137 /* Secure access */
142 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
143 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
144 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mt
222 uint32_t reg; tegra210_pmc_set_powergate() local
263 uint32_t reg; tegra_powergate_remove_clamping() local
306 uint32_t reg; tegra_powergate_is_powered() local
546 uint32_t reg; tegra210_pmc_attach() local
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-bx50v3.dtsi5 * This file is dual-licensed: you can use it either under the terms
43 #include "imx6q-ba16.dtsi"
46 mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <22000000>;
52 gpio-poweroff {
53 compatible = "gpio-poweroff";
58 reg_wl18xx_vmmc: regulator-wl18xx {
59 compatible = "regulator-fixed";
[all …]

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