Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
137 /* Secure access */
142 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
143 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
144 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
145 device_get_nameunit(_sc->dev), "tegra210_pmc", MTX_DEF)
146 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
147 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
148 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
173 {"nvidia,tegra210-pmc", 1},
192 if (sc->secure_access) {
195 device_printf(sc->dev," PMC SMC write failed: %lu\n",
199 bus_write_4(sc->mem_res, r, v);
207 if (sc->secure_access) {
210 device_printf(sc->dev," PMC SMC write failed: %lu\n",
215 return(bus_read_4(sc->mem_res, r));
222 uint32_t reg;
227 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
228 if (((reg != 0) && ena) || ((reg == 0) && !ena)) {
233 for (i = 100; i > 0; i--) {
234 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
235 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
240 device_printf(sc->dev,
246 for (i = 100; i > 0; i--) {
247 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
248 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
253 device_printf(sc->dev,
263 uint32_t reg;
274 reg = RD4(sc, PMC_PWRGATE_STATUS);
275 if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0)
286 for (i = 100; i > 0; i--) {
287 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
288 if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0)
293 device_printf(sc->dev, "Timeout when remove clamping\n");
295 reg = RD4(sc, PMC_CLAMP_STATUS);
296 if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0)
306 uint32_t reg;
310 reg = RD4(sc, PMC_PWRGATE_STATUS);
311 return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0);
324 device_printf(sc->dev, "Cannot set powergate: %d\n", id);
328 for (i = 100; i > 0; i--) {
334 device_printf(sc->dev, "Timeout when waiting on power up\n");
351 device_printf(sc->dev, "Cannot set powergate: %d\n", id);
354 for (i = 100; i > 0; i--) {
360 device_printf(sc->dev, "Timeout when waiting on power off\n");
376 device_printf(sc->dev, "Cannot assert reset\n");
382 device_printf(sc->dev, "Cannot stop clock\n");
388 device_printf(sc->dev, "Cannot power on powergate\n");
394 device_printf(sc->dev, "Cannot enable clock\n");
401 device_printf(sc->dev, "Cannot remove clamping\n");
406 device_printf(sc->dev, "Cannot unreset reset\n");
426 rv = OF_getencprop(node, "nvidia,suspend-mode", &tmp, sizeof(tmp));
430 sc->suspend_mode = TEGRA_SUSPEND_LP0;
434 sc->suspend_mode = TEGRA_SUSPEND_LP1;
438 sc->suspend_mode = TEGRA_SUSPEND_LP2;
442 sc->suspend_mode = TEGRA_SUSPEND_NONE;
447 rv = OF_getencprop(node, "nvidia,cpu-pwr-good-time", &tmp, sizeof(tmp));
449 sc->cpu_good_time = tmp;
450 sc->suspend_mode = TEGRA_SUSPEND_NONE;
453 rv = OF_getencprop(node, "nvidia,cpu-pwr-off-time", &tmp, sizeof(tmp));
455 sc->cpu_off_time = tmp;
456 sc->suspend_mode = TEGRA_SUSPEND_NONE;
459 rv = OF_getencprop(node, "nvidia,core-pwr-good-time", tmparr,
462 sc->core_osc_time = tmparr[0];
463 sc->core_pmu_time = tmparr[1];
464 sc->suspend_mode = TEGRA_SUSPEND_NONE;
467 rv = OF_getencprop(node, "nvidia,core-pwr-off-time", &tmp, sizeof(tmp));
469 sc->core_off_time = tmp;
470 sc->suspend_mode = TEGRA_SUSPEND_NONE;
473 sc->corereq_high =
474 OF_hasprop(node, "nvidia,core-power-req-active-high");
475 sc->sysclkreq_high =
476 OF_hasprop(node, "nvidia,sys-clock-req-active-high");
477 sc->combined_req =
478 OF_hasprop(node, "nvidia,combined-power-req");
479 sc->cpu_pwr_good_en =
480 OF_hasprop(node, "nvidia,cpu-pwr-good-en");
482 rv = OF_getencprop(node, "nvidia,lp0-vec", tmparr, sizeof(tmparr));
485 sc->lp0_vec_phys = tmparr[0];
486 sc->core_pmu_time = tmparr[1];
487 sc->lp0_vec_size = TEGRA_SUSPEND_NONE;
488 if (sc->suspend_mode == TEGRA_SUSPEND_LP0)
489 sc->suspend_mode = TEGRA_SUSPEND_LP1;
499 sc->secure_access = false;
502 * If PMC is coverd by secure trust zone, all reads returns 0,
508 sc->secure_access = true;
513 sc->secure_access = true;
526 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
546 uint32_t reg;
550 sc->dev = dev;
556 device_printf(sc->dev, "Cannot parse FDT data\n");
560 rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk);
562 device_printf(sc->dev, "Cannot get \"pclk\" clock\n");
567 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
569 if (sc->mem_res == NULL) {
577 reg = RD4(sc, PMC_CNTRL);
578 reg |= PMC_CNTRL_CPU_PWRREQ_OE;
579 WR4(sc, PMC_CNTRL, reg);
582 reg = RD4(sc, PMC_CNTRL);
583 if (sc->sysclkreq_high)
584 reg &= ~PMC_CNTRL_SYSCLK_POLARITY;
586 reg |= PMC_CNTRL_SYSCLK_POLARITY;
587 WR4(sc, PMC_CNTRL, reg);
590 reg = RD4(sc, PMC_CNTRL);
591 reg |= PMC_CNTRL_SYSCLK_OE;
592 WR4(sc, PMC_CNTRL, reg);
598 reg = RD4(sc, PMC_IO_DPD_STATUS);
599 reg &= ~ PMC_IO_DPD_STATUS_HDMI;
600 WR4(sc, PMC_IO_DPD_STATUS, reg);
602 reg = RD4(sc, PMC_IO_DPD2_STATUS);
603 reg &= ~ PMC_IO_DPD2_STATUS_HV;
604 WR4(sc, PMC_IO_DPD2_STATUS, reg);